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参数资料
| 型号： | W3E64M16S-333SBC |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | 10 X 12.50 MM, PLASTIC, BGA-60 |
| 文件页数： | 10/17页 |
| 文件大小： | 761K |
| 代理商： | W3E64M16S-333SBC |
2
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E64M16S-XSBX
January 2007
Rev. 5
TSOP Approach (mm)
22.3
11.9
64Mx16
66
TSOP
I/O
Count
I/O
Count
Area
265mm2
125mm2
53%
66 pins
60 Balls
9%
Area
2 x 125mm2 = 250mm2
125mm2
50%
2 x 60 balls = 120 balls
60 Balls
50%
S
A
V
I
N
G
S
Actual Size
W3E64M16S-XSBX
12.5
10
S
A
V
I
N
G
S
CSP Approach (mm)
60
FBGA
10.0
60
FBGA
12.5
Actual Size
W3E64M16S-XSBX
DENSITY COMPARISONS
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high
effective bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initial-
ized. The following sections provide detailed information
covering device initialization, register denition, command
descriptions and device operation.
10
10.0
12.5
相关PDF资料 |
PDF描述 |
|---|---|
| W3E64M72S-266SBC | 64M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| W3E64M72S-333SBI | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E64M72S-333SBM | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E64M72S-200SBC | 64M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| W3E64M72S-333SBC | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3E64M16S-333SBI | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 333 MHZ, 60 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E64M16S-333SBM | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 333 MHZ, 60 PBGA, MIL-TEMP. - Bulk |
| W3E64M72S-200BC | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-200BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-200BM | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
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