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参数资料
| 型号： | W3E64M16S-333SBC |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | 10 X 12.50 MM, PLASTIC, BGA-60 |
| 文件页数： | 15/17页 |
| 文件大小： | 761K |
| 代理商： | W3E64M16S-333SBC |
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E64M16S-XSBX
January 2007
Rev. 5
TABLE 1 – BURST DEFINITION
NOTES:
1.
For a burst length of two, A1-Ai select two-data-element block; A0 selects the
starting column within the block.
2.
For a burst length of four, A2-Ai select four-data-element block; A0-1 select the
starting column within the block.
3.
For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the
starting column within the block.
4.
Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
FIGURE 3 MODE REGISTER DEFINITION
M3 = 0
2
4
8
Reserved
M3 = 1
2
4
8
Reserved
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
00
Valid
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
Reserved
2.5
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Operating Mode
A10
A11
* M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
0*
BA0
BA1
Reserved
M9
M10
M11
0
10
0
--
-
A12
M12
0
-
issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. Otherwise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command will
be treated as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
process of precharging.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, but without requiring an explicit command. This is
accomplished by using A10 to enable AUTO PRECHARGE
in conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst. AUTO
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE command.
The device supports concurrent auto precharge if the
command to the other bank does not interrupt the data
transfer to the current bank.
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
0
0-1
1
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
相关PDF资料 |
PDF描述 |
|---|---|
| W3E64M72S-266SBC | 64M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| W3E64M72S-333SBI | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E64M72S-333SBM | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E64M72S-200SBC | 64M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| W3E64M72S-333SBC | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3E64M16S-333SBI | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 333 MHZ, 60 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E64M16S-333SBM | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 333 MHZ, 60 PBGA, MIL-TEMP. - Bulk |
| W3E64M72S-200BC | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-200BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-200BM | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
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