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参数资料
| 型号： | W3E64M16S-333SBC |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | 10 X 12.50 MM, PLASTIC, BGA-60 |
| 文件页数： | 17/17页 |
| 文件大小： | 761K |
| 代理商： | W3E64M16S-333SBC |
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E64M16S-XSBX
January 2007
Rev. 5
NOTES:
1.
CKE is HIGH for all commands shown except SELF REFRESH.
2.
A0-12 dene the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).
3.
A0-12 provide row address, and BA0, BA1 provide bank address.
4.
A0-9 provide column address; A10 HIGH enables the auto precharge feature (non
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
5.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
6.
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8.
Applies only to read bursts with auto precharge disabled; this command is
undened (and should not be used) for READ bursts with auto precharge enabled
and for WRITE bursts.
9.
DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR
SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering SELF REFRESH
and is automatically enabled upon exiting SELF REFRESH
(200 clock cycles must then occur before a READ
command can be issued). Input signals except CKE are
“Don’t Care” during SELF REFRESH. VREF voltage is also
required for the full duration of SELF REFRESH.
The procedure for exiting self refresh requires a sequence
of commands. First, CK and CK# must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for tXSNR,
because time is required for the completion of any internal
refresh in progress.
A simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for tXSNR time, then a DLL
Reset and NOPs for 200 additional clock cycles before
applying any other command.
* Self refresh available in commercial and industrial temperatures only.
TRUTH TABLE – COMMANDS (NOTE 1)
NAME (FUNCTION)
CS#
RAS#
CAS#
WE#
ADDR
DESELECT (NOP) (9)
H
X
NO OPERATION (NOP) (9)
L
H
X
ACTIVE (Select bank and activate row) ( 3)
L
H
Bank/Row
READ (Select bank and column, and start READ burst) (4)
L
H
L
H
Bank/Col
WRITE (Select bank and column, and start WRITE burst) (4)
L
H
L
Bank/Col
BURST TERMINATE (8)
L
H
L
X
PRECHARGE (Deactivate row in bank or banks) ( 5)
L
H
L
Code
AUTO REFRESH or SELF REFRESH (Enterselfrefreshmode) (6, 7)
L
H
X
LOAD MODE REGISTER (2)
L
Op-Code
TRUTH TABLE – DM OPERATION
NAME (FUNCTION)
DM
DQs
WRITE ENABLE (10)
L
Valid
WRITE INHIBIT (10)
H
X
相关PDF资料 |
PDF描述 |
|---|---|
| W3E64M72S-266SBC | 64M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| W3E64M72S-333SBI | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E64M72S-333SBM | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| W3E64M72S-200SBC | 64M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| W3E64M72S-333SBC | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W3E64M16S-333SBI | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 333 MHZ, 60 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E64M16S-333SBM | 制造商:Microsemi Corporation 功能描述:64M X 16 DDR, 2.5V, 333 MHZ, 60 PBGA, MIL-TEMP. - Bulk |
| W3E64M72S-200BC | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-200BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3E64M72S-200BM | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
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