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参数资料
| 型号： | W3HG128M72AEF665F1MCG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | DDR DRAM MODULE, DMA240 |
| 封装： | ROHS COMPLIANT, FBDIMM-240 |
| 文件页数： | 4/17页 |
| 文件大小： | 256K |
| 代理商： | W3HG128M72AEF665F1MCG |
12
W3HG128M72AEF-Fx
September 2007
Rev. 3
ADVANCED
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
VTX-DIFFp-p = 2 x|VTX-D+ -VTX-D-|
(EQ 1)
VTX-CM = DC(avg) of (|VTX-D+ +VTX-D-|/2)
(EQ 2)
VTX-CM-AC = ((Max|VTX-D+ +VTX-D-|)/2) - (Min |VTX-D++VTX-D-|)/2)
(EQ 3)
RTX-MATCH-DC = 2x ((|RTX-D+ -RTX-D-|)/(RTX-D++RTX-D-|))
(EQ 4)
DIFFERENTIAL TRANSMITTER OUTPUT SPECIFICATIONS
Parameter
Symbol
Values
Units
Comments
Min
Max
Maximum TX Drift (resync mode)
TTX-DRIFT-RESYNC
—
240
ps
16
Maximum TX Drift (resample mode only)
TTX-DRIFT-RESAMPLE
—
120
ps
16
Bit Error Ratio
BER
10-12
——
17
NOTES:
1.
Specied at the package pins into a timing and voltage compliance
test load as shown in Figure 4-2 and in steps outlined in 4.1.2.1 of the
JEDEC specication. Common-mode measurements to be performed
using a 101010 pattern.
2.
The transmitter designer should not articially elevate the common
mode in order to meet this specication.
3.
This is the ration of the VTX-DIFFp-p of the second and following bits
after a transition divided by the VTX-DIFFp-p of the rst bit after a
transition.
4.
De-emphasis shall be disabled in the calibration state.
5.
Includes all sources of AC common mode noise.
6.
Sinlge-ended voltages below that value that are simultaneously
detected on D+ and D- are interpreted as the Electrical Idle condition.
7.
The maximum value is specied to be at least (VTX-DIFFp-pL/4) +
(VTX-CM-ACp-p2).
8.
This number does not include the effects of SSC or reference clock
jitter.
9.
Dened as the expected maximum jitter for the given probability as
measured in the system (JJ), less the unbounded jitter
10.
Pulse width measure at 0V differential.
11.
One of the components that contribute to the deterioration of the
return loss is the ESB structure which needs to be carefully designed.
12.
The termination small signal resistance; tolerance across voltages
from 100 mV to 400 mV shall not exceed +/- 5 W with regard to the
average of the values measured at 100 mV and 400 mV for that pin.
13.
Lane to Lane skew at the Transmitter pins for an end component.
14.
Lane to Lane skew at the Transmitter pins or an intermediate
component (assuming zero Lane to Lane skew at the Receiver pins
of the incoming PORT).
15.
This is a static skew. An FBDIMM component is not allowed to
change its lane to lane phase relationship after initialization.
16.
Measured from the reference clock edge to the center of the output
eye. This specication must be met across specied voltage and
temperature ranges for a single component. Drift rate change is
signicantly below the tracking capability of the receiver.
17.
BER per differential lane.
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