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参数资料
| 型号： | W987Y6CBG80 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封装： | 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54 |
| 文件页数： | 6/46页 |
| 文件大小： | 1634K |
| 代理商： | W987Y6CBG80 |
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Preliminary W987Y6CB
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Device Deselect command
( CS ="H")
The Device Deselect command disables the command decoder so that the RAS , CAS , WE and
Address inputs are ignored. This command is similar to the No-Operation command.
Auto Refresh command
( RAS ="L", CAS ="L", WE ="H", CKE ="H", BS0, BS1, A0 to A11 = Don’t care)
The Auto Refresh command is used to refresh the row address provided by the internal refresh
counter. The Refresh operation must be performed 4096 times within 64ms. The next command
can be issued after tRC from the end of the Auto Refresh command. When the Auto Refresh
command is used, all banks must be in the idle state.
Self Refresh Entry command
( RAS ="L", CAS ="L", WE ="H", CKE="L", BS0, BS1, A0 to A11 = don’t care)
The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self
Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh
operation is automatically performed. Self Refresh mode is exited by taking CKE "high" (the Self
Refresh Exit command).
Self Refresh Exit command
(CKE = "H" during SDRAM in Self Refresh Mode)
This command is used to exit from Self Refresh mode. Any subsequent commands can be issued
after tRC from the end of this command.
Deep Power Down Mode Entry command
( RAS ="H", CAS ="H", WE ="L", CKE ="L", BS0, BS1, A0 to A11 = don’t care)
The Deep Power Down Mode Entry command is used to enter Deep Power Down mode. While
the device is in Deep Power Down mode, all internal circuits (except the CKE buffer) are disabled
in order to 10uA current consumption.
Deep Power Down Mode Exit command
(CKE= "H" during SDRAM in Deep Power Down Mode)
This command is used to exit from Deep Power Down mode. Full initialization is required when
the device exits from Deep Power Down Mode.
Data Write Enable /Disable command
(LDQM, UDQM ="L/H")
During a Write cycle, the LDQM or UDQM signal functions as Data Mask and can control every
word of the input data. The LDQM signal controls DQ0 to DQ7 and UDQM signal controls DQ8 to
DQ15.
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PDF描述 |
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| W989D6CBGX7E | 32M X 16 DDR DRAM, 5.4 ns, PBGA54 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W987Y6CBN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W987Z6CBN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W988D2FB | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPSDR |
| W988D2FBJX6E | 制造商:Winbond Electronics Corp 功能描述:IC LPSDR SDRAM 256MBIT 90VFBGA |
| W988D2FBJX6I | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPSDR |
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