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参数资料
| 型号： | W987Y6CBG80 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封装： | 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54 |
| 文件页数： | 8/46页 |
| 文件大小： | 1634K |
| 代理商： | W987Y6CBG80 |
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Preliminary W987Y6CB
- 16 -
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst operation.
Interruption
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is
interrupted, the remaining addresses are overridden by the new read address with the full burst
length. The data from the first Read Command continues to appear on the outputs until the CAS
latency from the interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command
will issue data on the first and second clocks cycles of the write operation, DQM is needed to
insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus
and DQM masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command.
When the previous burst is interrupted, the remaining addresses are overridden by the new
address and data will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before
the new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By
repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation
must be performed 4096 times (rows) within 64ms. The period between the Auto Refresh command
and the next command is specified by tRC.
The Self Refresh Mode is entered by issuing the Self Refresh Entry Command at the rising edge of
the clock. All banks must be idle prior to issuing the Self Refresh Entry Command. Once the command
is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has
entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is
internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh
operation after CKE is returned high. A minimum delay time is required when the device exits Self
Refresh Operation and before the next command can be issued. This delay is equal to the tRC cycle
time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W987Y6CBN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W987Z6CBN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W988D2FB | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPSDR |
| W988D2FBJX6E | 制造商:Winbond Electronics Corp 功能描述:IC LPSDR SDRAM 256MBIT 90VFBGA |
| W988D2FBJX6I | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPSDR |
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