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参数资料
| 型号： | WBLXT974BHCA8 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP160 |
| 封装： | ROHS COMPLIANT, PLASTIC, MS-002DD-1, HQFP-160 |
| 文件页数： | 7/76页 |
| 文件大小： | 1004K |
| 代理商： | WBLXT974BHCA8 |
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Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Datasheet
15
27
46
65
83
RX_DV0
RX_DV1
RX_DV2
RX_DV3
O
Receive Data Valid - Ports 0 - 3. These signals are synchronous to the respective
RX_CLKn. Active High indication that received code group maps to valid data.
29
48
67
85
RX_ER0
RX_ER1
RX_ER2
RX_ER3
O
Receive Error - Ports 0 - 3. These signals are synchronous to the respective RX_CLKn.
Active High indicates that received code group is invalid, or that PLL is not locked.
28
47
66
84
RX_CLK0
RX_CLK1
RX_CLK2
RX_CLK3
O
Receive Clock - Ports 0 - 3. 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.
37
57
75
93
COL0
COL1
COL2
COL3
O
Collision Detected - Ports 0 - 3. Active High outputs asserted upon detection of a collision.
Remain High for the duration of the collision. These signals are generated asynchronously.
Inactive during full-duplex operation.
38
58
76
94
CRS0
CRS1
CRS2
CRS3
O
Carrier Sense - Ports 0 - 3. Active High signals. During half-duplex operation
(bit 0.8 = 0), CRSn is asserted when either transmit or receive medium is non-idle. During
full-duplex operation (bit 0.8 = 1), CRSn is asserted only when the receive medium is non-
idle.
MII Control Interface Pins
97
MDIO
I/O
Management Data Input/Output. Bidirectional serial data channel for PHY/STA
communication.
98
MDINT
OD
Management Data Interrupt. An active Low output on this pin indicates status change.
Interrupt is cleared by sequentially reading Register 1, then Register 18.
99
MDC
I
Management Data Clock. Clock for the MDIO serial data channel.
Maximum frequency is 2.5 MHz.
100
MDDIS
I
Management Disable.
When MDDIS is High, the MDIO is restricted to Read Only and the Hardware Control
Interface pins provide continual control of their respective bits.
When MDDIS is Low at power up or Reset, the Hardware Control Interface pins control only
the initial or “default” values of their respective register bits. After the power-up/reset cycle is
complete, bit control reverts to the MDIO serial channel.
106
105
104
103
TRSTE0
TRSTE1
TRSTE2
TRSTE3
I
Tristate - Ports 0 - 3. This bit controls bit 0.10 (Isolate bit). When TRSTEn is High, the
respective port isolates itself from the MII Data Interface.
When MDDIS is High, TRSTE provides continuous control over bit 0.10.
When MDDIS is Low, TRSTE sets the initial (default) value of bit 0.10 at Reset and then bit
control reverts back to the MDIO interface.
Table 7.
LXT974 and LXT975 MII Signal Descriptions (Continued)
Pin#3
Symbol
Type1
Signal Description2
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
3. Unused pins should be tied Low.
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相关代理商/技术参数 |
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| WBLXT975BHC.A8 | 功能描述:IC ENET 10/100QUAD TXCVR 160HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| WBLXT9785EHC.D0865110 | 功能描述:IC TXRX 8PORT ETHERNET 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WBLXT9785EHC.D0-865110 | 制造商:Cortina Systems Inc 功能描述:PHY 8-CH 10Mbps/100Mbps 208-Pin PQFP |
| WBLXT9785EHC.D0-865111 | 制造商:Cortina Systems Inc 功能描述:PHY 8-CH 10Mbps/100Mbps 208-Pin PQFP |
| WBLXT9785HC.D0 | 功能描述:IC TXRX 8PORT ETHERNET 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
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