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Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.3 Media Independent
Interface (MII) Interfaces
4.3.1
Global MII Mode Select
The mode select pins are used for MII interface configuration settings upon power-up
sequencing. All ports are configured the same and cannot be intermixed.
4.3.2
Internal Loopback
Register bit 0.14 must be set to enable internal loopback operation. Register bits 16.14
and 0.8 must be set for 10 Mbps operation. Cortina recommends that auto-negotiation be
disabled while internal loopback is enabled. The normal auto-negotiation process code
word exchange cannot be completed.The following two-step sequence is recommended
for the most efficient mode change when enabling forced 100 Mbps internal loopback
mode directly from auto-negotiation mode:
1. Write Register 0 with 0x2100h (forced 100 Mbps), and
2. Write Register 0 with 0x6100h (enable internal loopback with forced 100 Mbps)
This two-step process ensures the 100 Mbps link comes up quickly. If the one-write
process of writing 0x6100h is followed, it may take up to 1.5 seconds before link is
established and data is received on the port. The 1.5 second delay is due to the IEEE
auto-negotiation Break Link Timer (BLT) requirement. The timer must expire before link is
established when changing modes directly from auto-negotiation to internal loopback
forced 100 Mbps mode. Use the above two-step process to eliminate the auto-negotiation
BLT timer requirement.
Table 41
MII Mode Select
Configuration
ModeSel1
ModeSel0
RMII1
00
SMII
0
1
SS-SMII
1
0
Reserved
1
1. Invalid for the BGA15 package.
Figure 8
Internal Loopback
Loopback
Digital
Block
Analog
Block
RMII/
SMII/
SS-
SMII
inter
face
Fx
Driver
Tx
Driver
LXT9785/9785E