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Cortina Systems LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.7 Serial MII Operation
4.7.6
Source Synchronous-Serial Media Independent Interface
Some system designs require the PHY to be placed between 3 to 12 inches away from
the MAC. A new Source Synchronous-Serial Media Independent Interface (SS-SMII)
definition has been added because of this requirement. To provide a source synchronous
interface between the PHY and MAC, the PHY must drive the RxCLK and the RxSYNC
signals to the MAC. Also, the MAC must drive the TxCLK and the TxSYNC signal to the
PHY. The REFCLK is also needed to synchronize the data to the PHY’s core clock
domain. TxData is clocked in using TxCLK and then synchronized to REFCLK and
transmitted to the twisted-pair. The RxData is synchronized to the RxCLK. See
Figure 23Table 44
RX Status Encoding Bit Definitions
Signal
Definition
CRS
Carrier Sense - identical to MII, except that it is not an asynchronous signal.
RxDV
Receive Data Valid - identical to MII. When RX_DV = 0, status
information is transmitted to the MAC. When RX_DV = 1,
received data is transmitted to the MAC.
0 = Status Byte
1 = Valid Data Byte
RxER
(RxData0)
Inter-frame status bit RxData0 indicates whether or not the
PHY detected an error somewhere in the previous frame.
0 = No Error
1 = Error
SPEED
(RxData1)
Inter-frame status bit RxData1 indicates port operating speed.
0 = 10 Mbps
1 = 100 Mbps
DUPLEX
(RxData2)
Inter-frame status bit RxData2 indicates port duplex condition.
0 = Half-duplex
1 = Full-duplex
LINK
(RxData3)
Inter-frame status bit RxData3 indicates port link status.
0 = Down
1 = Up
JABBER
(RxData4)
Inter-frame status bit RxData4 indicates port jabber status.
0 = OK
1 = Error
VALID
(RxData5)
Inter-frame status bit RxData5 conveys the validity of the upper
nibble of the last byte of the previous frame
0 = Invalid
1 = Valid
False Carrier
(RxData6)
Inter-frame status bit RxData6 indicates whether or not the
PHY has detected a false carrier event.
0 = No FC detected
1 = FC detected
RxData7
This bit is set to 1.
1 = Always
1. Both RxData0 and RxData5 bits are valid in the segment immediately following a frame, and remain valid
until the first data segment of the next frame begins.
Table 45
SS-SMII
Signal
To
From
Purpose
TxData
PHY
MAC
Transmit data & control
TxCLK
PHY
MAC
Transmit clock
TxSYNC
PHY
MAC
Synchronization pulses
RxData
MAC
PHY
Receive data & control
RxCLK
MAC
PHY
Receive clock
RxSYNC
MAC
PHY
Receive Synchronization
REFCLK
MAC
System
Synchronization