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参数资料
| 型号： | WED2ZL361MS26BC |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | SRAM |
| 英文描述： | 1M X 36 ZBT SRAM, 2.6 ns, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 8/12页 |
| 文件大小： | 645K |
| 代理商： | WED2ZL361MS26BC |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED2ZL361MS
Oct, 2002
Rev. 5
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC CHARACTERISTICS
NOTES:
1. All Address inputs must meet the specied setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is sampled valid. All other
synchronous inputs must meet the specied setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled.
3. A write cycle is dened by WE# low having been registered into the device at ADV Low. A Read cycle is dened by WE# High with ADV Low. Both cases must
meet setup and hold times.
OUTPUT LOAD (A)
OUTPUT LOAD (B)
(for tLZC, tLZOE, tHZOE, and tHZC)
Dout
Zo=50
RL=50
VL=1.25V
30pF*
Dout
1538
5pF*
+2.5V
1667
*Including Scope and Jig Capacitance
AC TEST CONDITIONS
(0 ≤ TA ≤ 70°C, VCC = 2.5V ± 5%; Commercial or -40°C ≤ Ta ≤ 85°C; VCC = 2.5V ± 5%; Industrial)
Parameter
Value
Input Pulse Level
0 to 2.5V
Input Rise and Fall Time (Measured at 20% to 80%)
1.0V/ns
Input and Output Timing Reference Levels
1.25V
Output Load
See Output Load (A)
Parameter
Symbol
250MHz
225MHz
200MHz
166MHz
150MHz
133MHz
Units
Min Max Min Max Min
Max
Min Max Min Max
Min
Max
Clock Time
tCYC
4.0
4.4
5.0
6.0
6.7
7.5
ns
Clock Access Time
tCD
--
2.6
--
2.8
--
3.0
--
3.5
--
3.8
--
4.2
ns
Output enable to Data Valid
tOE
--
2.6
--
2.8
--
3.0
--
3.5
--
3.8
--
4.2
ns
Clock High to Output Low-Z
tLZC
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Output Hold from Clock High
tOH
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Output Enable Low to output Low-Z
tLZOE
0.0
--
0.0
--
0.0
--
0.0
--
0.0
--
0.0
--
ns
Output Enable High to Output High-Z
tHZOE
--
2.6
--
2.8
--
3.0
--
3.0
--
3.0
--
3.5
ns
Clock High to Output High-Z
tHZC
--
2.6
--
2.8
--
3.0
--
3.0
--
3.0
--
3.5
ns
Clock High Pulse Width
tCH
1.7
--
2.0
--
2.0
--
2.2
--
2.2
--
2.2
--
ns
Clock Low Pulse Width
tCL
1.7
--
2.0
--
2.0
--
2.2
--
2.2
--
2.2
--
ns
Address Setup to Clock High
tAS
1.2
--
1.4
--
1.4
--
1.5
--
1.5
--
1.5
--
ns
CKE Setup to Clock High
tCES
1.2
--
1.4
--
1.4
--
1.5
--
1.5
--
1.5
--
ns
Data Setup to Clock High
tDS
1.2
--
1.4
--
1.4
--
1.5
--
1.5
--
1.5
--
ns
Write Setup to Clock High
tWS
1.2
--
1.4
--
1.4
--
1.5
--
1.5
--
1.5
--
ns
Address Advance to Clock High
tADVS
1.2
--
1.4
--
1.4
--
1.5
--
1.5
--
1.5
--
ns
Chip Select Setup to Clock High
tCSS
1.2
--
1.4
--
1.4
--
1.5
--
1.5
--
1.5
--
ns
Address Hold to Clock high
tAH
0.3
--
0.4
--
0.4
--
0.5
--
0.5
--
0.5
--
ns
CKE Hold to Clock High
tCEH
0.3
--
0.4
--
0.4
--
0.5
--
0.5
--
0.5
--
ns
Data Hold to Clock High
tDH
0.3
--
0.4
--
0.4
--
0.5
--
0.5
--
0.5
--
ns
Write Hold to Clock High
tWH
0.3
--
0.4
--
0.4
--
0.5
--
0.5
--
0.5
--
ns
Address Advance to Clock High
tADVH
0.3
--
0.4
--
0.4
--
0.5
--
0.5
--
0.5
--
ns
Chip Select Hold to Clock High
tCSH
0.3
--
0.4
--
0.4
--
0.5
--
0.5
--
0.5
--
ns
ZZ High to Power Down
tPDS
2
--
2
--
2
--
2
--
2
--
2
--
cycle
ZZ Low to Power Up
tPUS
2
--
2
--
2
--
2
--
2
--
2
--
cycle
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