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参数资料
| 型号： | WED3DL328V10BC |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA119 |
| 封装： | 14 X 22 MM, MO-163, BGA-119 |
| 文件页数： | 23/27页 |
| 文件大小： | 1195K |
| 代理商： | WED3DL328V10BC |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL328V
June, 2002
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
2
A0
0
0-1
1
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n = A0-A11/9/8
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
...Cn - 1,
Cn...
Not Supported
NOTES:
1. For full-page accesses: y = 2,048 (x4), y = 1,024 (x8), y = 512 (x16).
2. For a burst length of two, A1-A9, A11 (x4), A1-A9 (x8) or A1-A8 (x16) select the block-
of-two burst; A0 selects the starting column within the block.
3. For a burst length of four, A2-A9, A11 (x4), A2-A9 (x8) or A2-A8 (x16) select the block-
of-four burst; A0-A1 select the starting column within the block.
4. For a burst length of eight, A3-A9, A11 (x4), A3-A9 (x8) or A3-A8 (x16) select the block-
of-eight burst; A0-A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0-A9, A11 (x4), A0-A9 (x8) or A0-A8
(x16) select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) select the unique
column to be accessed, and mode register bit M3 is ignored.
BURST DEFINITION
FIG. 2 MODE REGISTER DEFINITION
M3 = 0
1
2
4
8
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Op Mode
A10
A11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = "0, 0"
to ensure compatibility
with future devices.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| WED3DL328V10BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BC | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V8BC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SDRAM|4X2MX32|CMOS|BGA|119PIN|PLASTIC |
| WED3DL328V8BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
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