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参数资料
| 型号： | WED3DL328V10BC |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA119 |
| 封装： | 14 X 22 MM, MO-163, BGA-119 |
| 文件页数： | 25/27页 |
| 文件大小： | 1195K |
| 代理商： | WED3DL328V10BC |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL328V
June, 2002
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Function
CKE
CE# RAS# CAS# WE# DQM
BA A10/AP
A9-0
A11
Notes
Previous
Cycle
Current
Cycle
Register
Mode Register Set
H
X
L
X
OP CODE
Refresh
Auto Refresh (CBR)
H
L
H
X
Entry Self Refresh
H
L
H
X
Precharge
Single Bank Precharge
H
X
L
H
L
X
BA
L
X
2
Precharge all Banks
H
X
L
H
L
X
H
X
Bank Activate
H
X
L
H
X
BA
Row Address
2
Write
H
X
L
H
L
X
BA
L
Column
2
Write with Auto Precharge
H
X
L
H
L
X
BA
H
Column
2
Read
H
X
L
H
L
X
BA
L
Column
2
Read with Auto Precharge
H
X
L
H
L
H
X
BA
H
Column
2
Burst Termination
H
X
L
H
L
X
3
No Operation
H
X
L
H
X
Device Deselect
H
X
H
X
Clock Suspend/Standby Mode
L
X
4
Data Write/Output Disable
H
X
L
X
5
Data Mask/Output Disable
H
X
H
X
5
Power Down Mode
Entry
X
L
H
X
6
Exit
X
H
X
6
COMMAND TRUTH TABLE
Notes:
1. All of the SDRAM operations are dened by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock.
2. Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS# latency.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One
clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled
and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the
clock is prohibited (zero clock latency).
All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations, therefore the device can’t
remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| WED3DL328V10BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BC | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V8BC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SDRAM|4X2MX32|CMOS|BGA|119PIN|PLASTIC |
| WED3DL328V8BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
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