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参数资料
| 型号： | WED3DL328V10BC |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA119 |
| 封装： | 14 X 22 MM, MO-163, BGA-119 |
| 文件页数： | 24/27页 |
| 文件大小： | 1195K |
| 代理商： | WED3DL328V10BC |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED3DL328V
June, 2002
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Parameter
Symbol
133MHz
125MHz
100MHz
Units
Min
Max
Min
Max
Min
Max
Clock Cycle Time (1)
CL = 3
tCC
7
1000
8
1000
10
1000
ns
CL = 2
tCC
7.5
1000
10
1000
12
1000
Clock to valid Output delay (1,2)
tSAC
5.4
6
7
ns
Output Data Hold Time (2)
tOH
3
ns
Clock HIGH Pulse Width (3)
tCH
2.5
3
ns
Clock LOW Pulse Width (3)
tCL
3
ns
Input Setup Time (3)
tSS
2
ns
Input Hold Time (3)
tSH
1
ns
CK to Output Low-Z (2)
tSLZ
1.0
ns
CK to Output High-Z
tSHZ
7
8
ns
Row Active to Row Active Delay (4)
tRRD
15
20
ns
RAS# to CAS# Delay (4)
tRCD
15
20
ns
Row Precharge Time (4)
tRP
20
24
ns
Row Active Time (4)
tRAS
50 120,000 50 120,000 60 120,000
ns
Row Cycle Time - Operation (4)
tRC
60
70
80
ns
Row Cycle Time - Auto Refresh (4,8)
tRFC
70
80
ns
Last Data in to New Column Address Delay (5)
tCDL
1
CK
Last Data in to Row Precharge (5)
tRDL
1
CK
Last Data in to Burst Stop (5)
tBDL
1
CK
Column Address to Column Address Delay (6)
tCCD
1.5
CK
Number of Valid OutputData (7)
2
ea
1
2
1
SDRAM AC CHARACTERISTICS
NOTES:
1.
Parameters depend on programmed CAS# latency.
2.
If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3.
Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4.
The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then
rounding up to the next higher integer.
5.
Minimum delay is required to complete write.
6.
All devices allow every cycle column address changes.
7.
In case of row precharge interrupt, auto precharge and read burst stop.
8.
A new command may be given trfc after self-refresh exit.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| WED3DL328V10BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BC | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V7BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
| WED3DL328V8BC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SDRAM|4X2MX32|CMOS|BGA|119PIN|PLASTIC |
| WED3DL328V8BI | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx32 SDRAM |
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