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参数资料
| 型号： | WEDPN8M72V-125BI |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 8M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, PBGA219 |
| 封装： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件页数： | 1/15页 |
| 文件大小： | 188K |
| 代理商： | WEDPN8M72V-125BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPN8M72V-XBX
November 2003 Rev. 13
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access ,memory using 5 chips containing
134,217,728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip’s 33,554,432-bit banks is organized as 4,096 rows by
512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column lo-
cation for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is com-
patible with the 2
n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.
8Mx72 Synchronous DRAM
! 40% SPACE SAVINGS
! Reduced part count
! Reduced I/O count
19% I/O Reduction
! Lower inductance and capacitance for low noise
performance
! Suitable for hi-reliability applications
! Upgradeable to 16M x 72 density (contact factory for
information)
FEATURES
BENEFITS
GENERAL DESCRIPTION
! High Frequency = 100, 125MHz
! Package:
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
! Single 3.3V ±0.3V power supply
! Fully Synchronous; all signals registered on positive
edge of system clock cycle
! Internal pipelined operation; column address can be
changed every clock cycle
! Internal banks for hiding row access/precharge
! Programmable Burst length 1,2,4,8 or full page
! 4096 refresh cycles
! Commercial, Industrial and Military Temperature Ranges
! Organized as 8M x 72
! Weight: WEDPN8M72V-XBX - 2.5 grams typical
* This product subject to change without notice.
Discrete Approach
ACTUAL SIZE
S
A
V
I
N
G
S
Area
5 x 265mm2 = 1328mm2
800mm2
40%
I/O
5 x 54 pins = 270 pins
219 Balls
19%
Count
25
32
11.9
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
White Electronic Designs
WEDPN8M72V-XBX
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相关代理商/技术参数 |
参数描述 |
|---|---|
| WEDPN8M72V-125BM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x72 SDRAM Module |
| WEDPN8M72V-133B2C | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133B2I | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133B2M | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133BC | 制造商:Microsemi Corporation 功能描述:8M X 72 SDRAM MODULE, 3.3V, 133 MHZ, 219 PBGA 25MM X 35MM, C - Bulk |
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