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参数资料
| 型号： | WEDPN8M72V-125BI |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 8M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, PBGA219 |
| 封装： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件页数： | 14/15页 |
| 文件大小： | 188K |
| 代理商： | WEDPN8M72V-125BI |
8
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WEDPN8M72V-XBX
ing I/Os will be High-Z two clocks later; if the DQM signal
was registered LOW, the I/Os will provide valid data.
The WRITE command is used to initiate a burst write access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 se-
lects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os is
written to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will be
written to memory; if the DQM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is is-
sued. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank is
to be precharged, inputs BA0, BA1 select the bank. Other-
wise BA0, BA1 are treated as “Don’t Care.” Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being is-
sued to that bank.
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specific READ or WRITE command. A precharge of
the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of
the READ or WRITE burst, except in the full-page burst
mode, where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled or
disabled for each individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated at
the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge time
(tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time.
The BURST TERMINATE command is used to truncate either
fixed-length or full-page bursts. The most recently registered
READ or WRITE command prior to the BURST TERMINATE
command will be truncated.
AUTO REFRESH is used during normal operation of the
SDRAM and is analagous to CAS-BEFORE-RAS (CBR) REFRESH
in conventional DRAMs. This command is nonpersistent, so
it must be issued each time a refresh is required.
The addressing is generated by the internal refresh control-
ler. This makes the address bits “Don’t Care” during an AUTO
REFRESH command. Each 128Mb SDRAM requires 4,096
AUTO REFRESH cycles every refresh period (tREF). Provid-
ing a distributed AUTO REFRESH command will meet the
refresh requirement and ensure that each row is refreshed.
Alternatively, 4,096 AUTO REFRESH commands can be is-
sued in a burst at the minimum cycle rate (tRC), once every
refresh period (tREF).
The SELF REFRESH command can be used to retain data in
the SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the SDRAM retains data with-
out external clocking. The SELF REFRESH command is initi-
ated like an AUTO REFRESH command except CKE is dis-
abled (LOW). Once the SELF REFRESH command is regis-
tered, all the inputs to the SDRAM become “Don’t Care,”
with the exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain
in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock is
defined as a signal cycling within timing constraints speci-
fied for the clock pin) prior to CKE going back HIGH. Once
CKE is HIGH, the SDRAM must have NOP commands is-
sued (a minimum of two clocks) for tXSR, because time is
WRITE
PRECHARGE
AUTO PRECHARGE
BURST TERMINATE
AUTO REFRESH
SELF REFRESH*
相关PDF资料 |
PDF描述 |
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| WEDPN8M72VR-66I | 8M X 72 SYNCHRONOUS DRAM MODULE, 7.5 ns, PBGA219 |
| WG1602B-Y-JCS | WP1602B-Y-JCS |
| WG160PRW40 | TWO PART BOARD CONNECTOR |
| WG2002A-Y-JCS | WP2002A-Y-JCS |
| WG92SAW24SY-1 | 92 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, WIRE WRAP, RECEPTACLE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WEDPN8M72V-125BM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x72 SDRAM Module |
| WEDPN8M72V-133B2C | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133B2I | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133B2M | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133BC | 制造商:Microsemi Corporation 功能描述:8M X 72 SDRAM MODULE, 3.3V, 133 MHZ, 219 PBGA 25MM X 35MM, C - Bulk |
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