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参数资料
| 型号： | WEDPN8M72V-125BI |
| 厂商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分类： | DRAM |
| 英文描述： | 8M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, PBGA219 |
| 封装： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件页数： | 10/15页 |
| 文件大小： | 188K |
| 代理商： | WEDPN8M72V-125BI |
4
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WEDPN8M72V-XBX
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0 and BA1 select the bank, A0-11 select the
row). The address bits (A0-8) registered coincident with
the READ or WRITE command are used to select the start-
ing column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information cover-
ing device initialization, register definition, command de-
scriptions and device operation.
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those speci-
fied may result in undefined operation. Once power is ap-
plied to VDD and VDDQ (simultaneously) and the clock is
stable (stable clock is defined as a signal cycling within tim-
ing constraints specified for the clock pin), the SDRAM re-
quires a 100s delay prior to issuing any command other
than a COMMAND INHIBIT or a NOP. Star ting at some point
during this 100s period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.
Once the 100s delay has been satisfied with at least one COM-
MAND INHIBIT or NOP command having been applied, a
PRECHARGE command should be applied. All banks must
be precharged, thereby placing the device in the all banks
idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete, the
SDRAM is ready for Mode Register programming. Because the
Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.
The Mode Register is used to define the specific mode of
operation of the SDRAM. This definition includes the selec-
tion of a burst length, a burst type, a CAS latency, an oper-
ating mode and a write burst mode, as shown in Figure 3.
The Mode Register is programmed via the LOAD MODE REG-
ISTER command and will retain the stored information until
it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4-
M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the WRITE burst mode, and M10
and M11 are reserved for future use.
The Mode Register must be loaded when all banks are idle,
and the controller must wait the specified time before initi-
ating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in Fig-
ure 3. The burst length determines the maximum number of
column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4 or 8 locations are
available for both the sequential and the interleaved burst
types, and a full-page burst is available for the sequential
type. The full-page burst is used in conjunction with the
BURST TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown opera-
tion or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of col-
umns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-8 when the
burst length is set to two; by A2-8 when the burst length is
set to four; and by A3-8 when the burst length is set to
eight. The remaining (least significant) address bit(s) is (are)
used to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is reached.
INITIALIZATION
The 512Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, in-
cluding the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability
to interleave between internal banks in order to hide
precharge time and the capability to randomly change col-
umn addresses on each clock cycle during a burst access.
FUNCTIONAL DESCRIPTION
REGISTER DEFINITION
MODE REGISTER
BURST LENGTH
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| WG1602B-Y-JCS | WP1602B-Y-JCS |
| WG160PRW40 | TWO PART BOARD CONNECTOR |
| WG2002A-Y-JCS | WP2002A-Y-JCS |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| WEDPN8M72V-125BM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x72 SDRAM Module |
| WEDPN8M72V-133B2C | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133B2I | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133B2M | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-133BC | 制造商:Microsemi Corporation 功能描述:8M X 72 SDRAM MODULE, 3.3V, 133 MHZ, 219 PBGA 25MM X 35MM, C - Bulk |
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