参数资料
型号: WJLXT361LEA2
厂商: INTEL CORP
元件分类: 数字传输电路
英文描述: DATACOM, PCM TRANSCEIVER, PQFP44
封装: 10 X 10MM, LQFP-44
文件页数: 37/55页
文件大小: 1045K
代理商: WJLXT361LEA2
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
42
Datasheet
Table 31. Receive Timing Characteristics for T1 Operation (See Figure 15)
Parameter
Sym
Min
Typ1
Max
Unit
Receive clock duty cycle
2, 3
RLCKd
40
50
60
%
Receive clock pulse width 2, 3
tPW
–648
ns
Receive clock pulse width high
tPWH
–324
ns
Receive clock pulse width low1,3
tPWL
260
324
388
ns
RPOS/RNEG to RCLK rising time
tSUR
–274
ns
RCLK rising to RPOS/RNEG hold time
tHR
–274
ns
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles are
for worst case jitter conditions.
3. Worst case conditions guaranteed by design only.
Table 32. Receive Timing Characteristics for E1 Operation (See Figure 15)
Parameter
Sym
Min
Typ
1
Max
Unit
Receive clock duty cycle
2, 3
RLCKd
40
50
60
%
Receive clock pulse width 2, 3
tPW
–488
ns
Receive clock pulse width high
tPWH
–244
ns
Receive clock pulse width low1,3
tPWL
195
244
293
ns
RPOS/RNEG to RCLK rising time
tSUR
–194
ns
RCLK rising to RPOS/RNEG hold time
tHR
–194
ns
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz.)
3. Worst case conditions guaranteed by design only.
Figure 15. Receive Clock Timing
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