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| 型号： | WJLXT361LEA2 |
| 厂商： | INTEL CORP |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP44 |
| 封装： | 10 X 10MM, LQFP-44 |
| 文件页数： | 6/55页 |
| 文件大小： | 1045K |
| 代理商： | WJLXT361LEA2 |
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LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
14
Datasheet
3.2.2
Transmit Monitoring
The transmitter includes a short circuit limiter that limits the current sourced into a low impedance
load. The limiter automatically resets when the load current drops below the limit. The current is
determined by the interface circuitry (total resistance on transmit side).
The Performance Status Register (PSR) flags open circuits in bit PSR.DFMO. A transition of
DFMO can provide an interrupt, and its transition sets bit TSR.DFMO = 1. Writing a 1 in bit
ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.
3.2.3
Transmit Drivers
The transceiver transmits data as a 50% line code as shown in Figure 3. To reduce power
consumption, the line driver is active only during transmission of marks, and is disabled during
transmission of spaces. Biasing of the transmit DC level is on-chip.
3.2.4
Transmit Idle Mode
Transmit Idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, Transmit Idle mode becomes active, and TTIP and
TRING change to the high impedance state. Remote loopback, Dual loopback, TAOS, or detection
of Network Loop Up code in the receive direction, temporarily disable the high impedance state.
3.2.5
Transmit Pulse Shape
As shown in Table 8 on page 27, the transmitted pulse shape is established by bits EC1 through
EC4 of Control Register #1 (CR1).
Shaped pulses meeting the various T1, DS1, DSX-1 and E1 specifications are applied to the AMI
line driver for transmission onto the line at TTIP and TRING. The transceiver produces DSX-1
pulses for Short-Hual T1 applications (settings from 0 dB to +6.0 dB of cable), DS1 pulses for
Long-Hual T1 applications (settings from 0 dB to -22.5 dB), and a G.703 pulse for E1 applications.
Refer to the Test Specifications section for pulse mask specifications.
Figure 3. 50% Duty Cycle Coding
10
1
Bit Cell
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