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| 型号： | WJLXT901ALCA4 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 9/48页 |
| 文件大小： | 621K |
| 代理商： | WJLXT901ALCA4 |
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Intel
LXT901A/907A Universal 3.3 V Ethernet Transceiver
Datasheet
17
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
2.4
Loopback Functions
2.4.1
Standard TP Loopback
The LXT901A/907A Transceiver provides the standard loopback function defined by the
10BASE-T specification for the twisted-pair port. The loopback function operates in conjunction
with the transmit function. Data transmitted by the back-end is internally looped back within the
LXT901A/907A Transceiver from the TXD pin through the Manchester encoder/decoder to the
RXD pin and returned to the back-end. This standard loopback function is disabled when a data
collision occurs, clearing the RXD circuit for the TPI data. Standard loopback is also disabled
during link fail and jabber states. The LXT901A/907A Transceiver also provides three additional
loopback functions.
2.4.2
Forced TP Loopback
“Forced” twisted-pair loopback is controlled by the LBK pin. When the twisted-pair port is
selected and LBK is High, twisted-pair loopback is “forced”, overriding collisions on the twisted-
pair circuit. When LBK is Low, normal loopback is in effect.
2.4.3
AUI Loopback
AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High,
data transmitted by the back-end is internally looped back from the TXD pin through the
Manchester encoder/decoder to the RXD pin. When LBK is Low, no AUI loopback occurs.
2.4.4
External Loopback
An external loopback mode, useful for system-level testing, is controlled by the LEDC/FDE pin.
When LEDC/FDE is tied Low, the LXT901A/907A Transceiver disables the collision detection
and internal loopback circuits, to allow external loopback. External loopback mode can be set on
either twisted-pair or AUI ports.
2.5
Link Integrity Test Function
Figure 7 on page 18 is a state diagram of the LXT901A/907A Transceiver Link Integrity test
function. The link integrity test is used to determine the status of the receive side twisted-pair
cable. Link integrity testing is enabled when the LI pin is tied High. When enabled, the receiver
recognizes link integrity pulses which are transmitted in the absence of receive traffic. If no serial
data stream or link integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state
and disables the transmit and normal loopback functions. The LXT901A/907A Transceiver ignores
any link integrity pulse with an interval less than 2 - 7 ms. The LXT901A/907A Transceiver
remains in the link fail state until it detects either a serial data packet or two or more link integrity
pulses.
相关PDF资料 |
PDF描述 |
|---|---|
| WJLXT907ALCA4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT905LC.C2 | DATACOM, ETHERNET TRANSCEIVER, PQFP32 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| WJLXT901ALCA4-865823 | 制造商:Cortina Systems Inc 功能描述:WJLXT901ALC.A4-865823 |
| WJLXT905LC.C2 | 功能描述:IC 10BASE-T TXCVR 3V/5V 32-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WJLXT905LC.C2 S E001 | 制造商:Intel 功能描述:UNIVERSAL 10BASE-T TRANSCEIVER WITH 3.3 V SUPPORT |
| WJLXT905LC.C2-863532 | 制造商:Cortina Systems Inc 功能描述:PN may be NE SA CE AP NA SE 制造商:Cortina Systems 功能描述:PN may be NE SA CE AP NA SE |
| WJLXT905LC.C2-863540 | 制造商:Cortina Systems Inc 功能描述:UNIVERSAL 10BASE-T TRANSCEIVER WITH 3.3 V SUPPORT 制造商:Cortina Systems 功能描述:UNIVERSAL 10BASE-T TRANSCEIVER WITH 3.3 V SUPPORT |
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