参数资料
型号: WJLXT908LC.A4
厂商: INTEL CORP
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: ROHS COMPLIANT, LQFP-64
文件页数: 16/46页
文件大小: 618K
代理商: WJLXT908LC.A4
Intel
LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver
Datasheet
23
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct-2005
3.2.4
Manual Port Select & Link Test Function
When MD2:0 = Low, High, Low, the Intel
LXT908 Universal 3.3 V 10BASE-T and AUI
Transceiver logic and framing are set to Mode 3 (compatible with Fujitsu MB86950 and
MB86960, and Seeq 8005 controllers). Figure 12 shows the setup for Fujitsu controllers. Figure 13
on page 24 shows the four inverters required to interface with the Seeq 8005 controller. As in
Figure 9 on page 20, both these Mode 3 applications show the LI pin tied High, enabling Link
Testing; and the NTH and DSQE pins are both tied High, selecting the standard receiver threshold
and disabling SQE. However, in these applications, AUTOSEL is tied Low, allowing external port
selection through the PAUI pin.
Figure 12. LAN Adapter Board - Manual Port Select with Link Test Function
LX
T
9
0
8
20 MHz
20 pF
CLKI
TXD
TPIN
100
Ω
TPIP
1 : 1
116
14
6
5
4
3
2
1
11
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To
1
0
B
A
S
E
-T
TW
IS
TE
D
-
PAI
R
N
E
T
W
O
R
K
1
2
4
5
7
89
10
12
13
15
16
1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
D
-
CO
NNE
CT
O
R
t
o
A
U
ID
R
O
P
C
ABL
E
Chassis
Gnd
Fuse
1
78
Ω
78
Ω
78
Ω
12.4 k
Ω
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
MD2
DSQE
LI
JAB
PLR
TXD
TEN
TCKN
RCKN
RXD
XCD
LBC
Red
MB86950 or MB86960
BACK-END/
CONTROLLER
INTERFACE
PROGRAMMING
OPTIONS
LINE STATUS
1 %
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
330
1 : 2
Green
330
Port Selection
TEST
11.5
Ω 1%
11.5
Ω 1%
XCOL
MD1
MD0
MODE
SELECT
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
1
220pF
0.1
μF
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