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参数资料
| 型号： | WJLXT908LC.A4 |
| 厂商： | INTEL CORP |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 46/46页 |
| 文件大小： | 618K |
| 代理商： | WJLXT908LC.A4 |
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Intel
LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver
Datasheet
9
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct-2005
Table 1.
Signal Descriptions (Sheet 1 of 3)
Pin#
Symbol
I/O
Description
PLCC
LQFP
1
34
10
56
VCC1
VCC2
–
Power 1 and 2. Connect to positive power supply terminal (+3.3V
DC).
–
9
VCCA
–
Analog Supply. (+3.3V)
2
3
11
12
CIP
CIN
I
AUI Collision Pair. Differential input pair connected to the AUI
transceiver CI circuit. The input is collision signaling or SQE.
413
NTH
I
Normal Threshold. When NTH is High, the normal TP squelch
threshold is in effect. When NTH is Low, the normal TP squelch
threshold is reduced by 4.5 dB.
5
6
25
14
15
44
MD0
MD1
MD2
I
Mode Select 0 (MD0), Mode Select 1 (MD1) and Mode Select 2
(MD2). Mode select pins determine the controller compatibility
mode as specified in Table 2 on page 13.
7, 29
1, 2, 6,
16, 17,
18, 20,
30, 31,
32, 33,
41, 43,
48, 49,
50, 51,
60, 63,
64
N/C
–
No Connect. These pins may be left unconnected or tied to ground.
819
LI
I
Link Test Enable. Controls Link Integrity Test; enabled when High,
disabled when Low.
921
JAB
O
Jabber Indicator. Output goes High to indicate Jabber state.
10
22
TEST
I
Test. This pin must be tied High.
11
23
TCLK
O
Transmit Clock. A 10 MHz clock output. This clock signal should
be directly connected to the transmit clock input of the controller.
TCLK goes to high impedance (tri-state) when LEDT/PDN is pulled
Low externally.
12
24
TXD
I
Transmit Data. Input signal containing NRZ data to be transmitted
on the network. TXD is connected directly to the transmit data
output of the controller.
13
25
TEN
I
Transmit Enable. Enables data transmission and starts the Watch-
Dog Timer. Synchronous to TCLK (see Test Specifications for
details).
14
15
26
27
CLKO
CLKI
O
I
Crystal Oscillator. A 20 MHz crystal must be connected across
these pins, or a 20 MHz clock applied at CLKI, with CLKO left open.
16
28
COL
O
Collision Detect. Output driving the collision detect input of the
controller. COL goes to high impedance (tri-state) when LEDT/PDN
is pulled Low externally.
17
29
AUTOSEL
I
Automatic Port Select. When High, automatic port selection is
enabled (the Intel LXT908 Universal 3.3 V 10BASE-T and AUI
Transceiver defaults to the AUI port only if TP link
integrity = Fail). When Low, manual port selection is enabled (the
PAUI pin determines the active port).
18
34
LEDR
O
Receive LED. Open drain driver for the receive indicator LED.
Output is pulled Low during receive, except when data is being
looped back to DIN/DIP from a remote transceiver (external MAU).
LED “On” time (Low output) is extended by approximately 100 ms.
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