参数资料
型号: WJLXT908LC.A4
厂商: INTEL CORP
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: ROHS COMPLIANT, LQFP-64
文件页数: 2/46页
文件大小: 618K
代理商: WJLXT908LC.A4
Intel
LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver
10
Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct-2005
19
35
LEDT/
PDN
O
I
Transmit LED (LEDT)/Power Down (PDN). Open drain driver for
the transmit indicator LED. Output is pulled Low during transmit. Do
not allow this pin to float. If unused, tie High. LED “On” time
(Low output) is extended by approximately 100 ms. If externally tied
Low, the Intel LXT908 Universal 3.3 V 10BASE-T and AUI
Transceiver goes to power-down state. In power-down state, TCLK,
COL, RXD, CD, and RCLK (pins 11, 16, 26, 27, and 28,
respectively) are tri-stated.
20
36
LEDL
O
I
Link LED. Open drain driver for link integrity indicator LED. Output
is pulled Low during link test pass. If externally tied Intel LXT908
Universal 3.3 V 10BASE-T and AUI Transceiver Low, internal
circuitry is forced to “Link Pass” state and the Intel LXT908
Universal 3.3 V 10BASE-T and AUI Transceiver will continue to
transmit link test pulses.
21
37
LEDC/
FDE
O
I
Collision LED (LEDC)/Full Duplex Enable (FDE). Open drain
driver for the collision indicator LED pulls Low during collision. LED
“On” time (Low output) is extended by approximately 100 ms. If
externally tied Low, the Intel LXT908 Universal 3.3 V 10BASE-T
and AUI Transceiver disables the internal TP loopback and collision
detection circuits to allow full-duplex operation or external twisted-
pair loopback.
22
38
LBK
I
Loopback. Enables internal loopback mode. Refer to Functional
Description and Test Specifications for details.
23
33
39
55
GND1
GND2
Ground Returns 1 and 2. Connect to negative power supply
terminal (ground).
40
GNDA
Analog Ground. Ground for analog plane.
24
42
RBIAS
I
Bias Control. A 12.4 k
Ω 1% resistor to ground at this pin controls
operating circuit bias.
26
45
RXD
O
Receive Data. Output signal connected directly to the receive data
input of the controller. RXD goes to high impedance (tri-state) when
LEDT/PDN is pulled Low externally.
27
46
CD
O
Carrier Detect. An output to notify the controller of activity on the
network. CD goes to high impedance (tri-state) when LEDT/PDN is
pulled Low externally.
28
47
RCLK
O
Receive Clock. A recovered 10 MHz clock that is synchronous to
the received data and connected to the controller receive clock
input. RCLK goes to high impedance (tri-state) when LEDT/PDN is
pulled Low externally.
30
52
PLR
O
Polarity Reverse. Output goes High to indicate reversed polarity at
the TP input.
32
35
31
36
54
57
53
58
TPOPA
TPONA
TPOPB
TPONB
O
Twisted-Pair Transmit Pairs A & B. Two differential driver pair
outputs (A and B) to the twisted-pair cable. The outputs are pre-
equalized. Each pair must be shorted together with an 11.5
Ω 1%
resistor to match an impedance of 100
Ω.
37
59
DSQE
I
Disable SQE. When DSQE is High, the SQE function is disabled.
When DSQE is Low, the SQE function is enabled. SQE must be
disabled for normal operation in Hub/Switch applications.
3839
61
62
TPIP
TPIN
I
Twisted-Pair Receive Pair. A differential input pair from the TP
cable. Receive filter is integrated on chip. No external filters are
required.
Table 1.
Signal Descriptions (Sheet 2 of 3)
Pin#
Symbol
I/O
Description
PLCC
LQFP
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