参数资料
型号: X40435V14I-CT1
厂商: Intersil
文件页数: 6/26页
文件大小: 0K
描述: IC VOLT MON TRPL EEPROM 14-TSSOP
标准包装: 2,500
类型: 多压监控器
监视电压数目: 3
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 可调节/可选择
电压 - 阀值: 1V,2.9V,4.6V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 带卷 (TR)
X40430, X40431, X40434, X40435
PIN CONFIGURATION
X40430, X40434
14 Ld SOIC, TSSOP
X40431, X40435
14 Ld SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
MR
RESET
V SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V CC
WDO
V3FAIL
V3MON
WP
SCL
SDA
V2FAIL
V2MON
LOWLINE
NC
MR
RESET
V SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V CC
WDO
V3FAIL
V3MON
WP
SCL
SDA
PIN DESCRIPTION
Pin
1
Name
V2FAIL
Function
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V TRIP2 and goes
HIGH when V2MON exceeds V TRIP2 . There is no power-up reset delay circuitry on this pin.
2 V2MON
V2 Voltage Monitor Input. When the V2MON input is less than the V TRIP2 voltage, V2FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
second power supply with no external components. Connect V2MON to V SS or V CC when not used. The
V2MON comparator is supplied by V2MON (X40430, X40431) or by the V CC input (X40434, X40435).
3 LOWLINE Early Low V CC Detect. This CMOS output signal goes LOW when V CC < V TRIP1 and goes high when
V CC > V TRIP1 .
4 NC
5 MR
6 RESET/
RESET
7 V SS
8 SDA
9 SCL
10 WP
11 V3MON
12 V3FAIL
13 WDO
14 V CC
No connect.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the t PURST thereafter.
RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when-
ever V CC falls below V TRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t PURST ) on power-up. It will also stay active until manual reset is released and for
t PURST thereafter.
RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-
ever V CC falls below V TRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t PURST ) on power-up. It will also stay active until manual reset is released and for
t PURST thereafter.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10M ? typical).
V3 Voltage Monitor Input. When the V3MON input is less than the V TRIP3 voltage, V3FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to V SS or V CC when not used. The
V3MON comparator is supplied by the V3MON input.
V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than V TRIP3 and goes
HIGH when V3MON exceeds V TRIP3 . There is no power-up reset delay circuitry on this pin.
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Supply Voltage
6
FN8251.1
May 24, 2006
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