参数资料
| 型号： | X4C105V20I |
| 厂商： | Intersil |
| 文件页数： | 4/14页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR NOVRAM/EE 20-TSSOP |
| 标准包装： | 75 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.875V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
X4C105
Serial Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus. See Figure 2.
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data. Refer to Figure 4.
The device will respond with an acknowledge after
recognition of a start condition and if the correct device
identifier and select bits are contained in the slave address
byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
eight bit word. The device will acknowledge all incoming data
and address bytes, except for the slave address byte when
the device identifier and/or select bits are incorrect or when
the device is busy, such as during a nonvolatile write.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
standby mode and place the device into a known state.
Serial Write Operations
Byte Write
For a write operation, the device requires the slave address
byte and a word address byte. This gives the master access to
any one of the words in the array. After receipt of the word
address byte, the device responds with an acknowledge, and
awaits the next eight bits of data. After receiving the 8 bits of the
data byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating a stop
condition, at which time the device begins the internal write
cycle to the nonvolatile memory. During this internal write cycle,
the device inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 5.
An attempted write to a protected block of memory will
suppress the acknowledge bit and the operation will
terminate.
SCL
SDA
START
STOP
FIGURE 3. VALID START AND STOP CONDITIONS
SCL
FROM
1
8
9
MASTER
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM
RECEIVER
START
4
FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVE
ACKNOWLEDGE
FN8124.2
July 3, 2008
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