参数资料
| 型号： | X4C105V20I |
| 厂商： | Intersil |
| 文件页数： | 7/14页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR NOVRAM/EE 20-TSSOP |
| 标准包装： | 75 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.875V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
X4C105
The device offers a similar operation, called “Set Current
Address,” where the device ends the transmission and issues
a stop instead of the second start, shown in Figure 10. The
device goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This operation
loads the new address into the address counter. The next
current address read operation will then read from the newly
loaded address. This operation could be useful if the master
knows the next address it needs to read, but is not ready for
the data.
Sequential Read
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
? a device type identifier that is always ‘1010’.
? two bits that provide the device select bits.
? one bit that becomes the MSB of the address.
? one bit of the slave command byte is a R/W bit. The R/W
bit of the slave address byte defines the operation to be
performed. When the R/W bit is a one, then a read
operation is selected. A zero selects a write operation.
Refer to Figure 11.
After loading the entire slave address byte from the SDA
bus, the device compares the device select bits with the
status of the device select pins. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Slave Byte
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
1
0
1
0
S2
S1
A8
R/W
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address counter
for read operations increments through all page and column
addresses, allowing the entire memory contents to be serially
read during one operation. At the end of the address space
the counter “rolls over” to address 0000 H and the device
continues to output data for each acknowledge received.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter is
undefined on a power-up condition.
Write Protect Operations
The WP pin provides write protection. The WP pin protects
the upper half of the array.
TABLE 1. WRITE PROTECTED AREAS
Refer to Figure 11 for the acknowledge and data transfer
sequence.
Serial Device Addressing
Slave Address Byte
Following a start condition, the master must output a slave
address byte. This byte consists of several parts:
WP PIN
LOW
HIGH
SERIAL MEMORY WRITE PROTECTION
Writes possible to all locations
No writes to 100H-1FFH, writes possible to 000H to 0FFH
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
A
R
T
SLAVE
ADDRESS
S
T
O
P
SDA BUS
0
1
A
A
A
SIGNALS
FROM THE
C
K
C
K
C
K
DATA
SLAVE
FIGURE 10. RANDOM ADDRESS READ SEQUENCE
SIGNALS
FROM THE
MASTER
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
S
T
O
P
SDA BUS
1
A
C
SIGNALS
FROM THE
K
DATA
(1)
DATA
(2)
DATA
(n - 1)
DATA
(n)
SLAVE
(“n” IS ANY INTEGER GREATER THAN 1)
FIGURE 11. SEQUENTIAL READ SEQUENCE
7
FN8124.2
July 3, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| X4C105V20I-VTRIP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
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