参数资料
| 型号： | X9110TV14ZT1 |
| 厂商： | Intersil |
| 文件页数： | 16/18页 |
| 文件大小： | 0K |
| 描述： | IC XDCP 1024-TAP 100K 14-TSSOP |
| 标准包装： | 2,500 |
| 系列： | XDCP™ |
| 接片： | 1024 |
| 电阻（欧姆）： | 100k |
| 电路数： | 1 |
| 温度系数： | 标准值 ±300 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | 4 线 SPI（芯片选择，设备位址） |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
7
FN8158.3
February 13, 2008
Write in Process (WIP bit)
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
a Write In Process bit (WIP). The WIP bit is read with a Read
Status command (See Figure 4).
Power-up and Down Requirements
At all times, the V+ voltage must be greater than or equal to
the voltage at RH or RL, and the voltage at RH or RL must be
greater than or equal to the voltage at V-. During power-up
and power-down, VCC, V+, and V- must reach their final
values within 1msec of each other.
ID3
ID2
ID1
ID0
0
A0
I2
I1
I0
RB
RA
SCK
SI
CS
0101
R/W
DEVICE ID
INTERNAL
INSTRUCTION
OPCODE
ADDRESS
REGISTER
0
ADDRESS
0
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
ID3 ID2 ID1 ID0 0
A0 R/W I2
00
SCK
SI
0
X
X0
0
XX
X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
I1
I0 0 RB RA
0
101
0
XX
X
DEVICE ID
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
WIPER
POSITION
0
FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
ID3 ID2 ID1 ID0 0
A0 R/W I2
00
SCK
SI
1
0
X
X0
0
XX
X
WIP
CS
I1
I0
0 RB RA
01
0
1
0
XX
X
DEVICE ID
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
STATUS
BIT
X X
0
00
0 0
0
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
X9110
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相关代理商/技术参数 |
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|---|---|
| X9111 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Single Supply/Low Power/1024-Tap/SPI Bus |
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