参数资料
型号: XA3S250E-4PQG208I
厂商: XILINX INC
元件分类: FPGA
英文描述: FPGA, 612 CLBS, 250000 GATES, 572 MHz, PQFP208
封装: LEAD FREE, PLASTIC, QFP-208
文件页数: 4/37页
文件大小: 717K
代理商: XA3S250E-4PQG208I
DS635 (v2.0) September 9, 2009
Product Specification
12
R
Table 10: DC Characteristics of User I/Os Using
Single-Ended Standards
IOSTANDARD
Attribute
Test
Conditions
Logic Level
Characteristics
IOL
(mA)
IOH
(mA)
VOL
Max (V)
VOH
Min (V)
LVTTL(3)
2
–2
0.4
2.4
44
–4
66
–6
88
–8
12
–12
16
–16
LVCMOS33(3)
2
–2
0.4
VCCO 0.4
44
–4
66
–6
88
–8
12
–12
16
–16
LVCMOS25(3)
2
–2
0.4
VCCO 0.4
44
–4
66
–6
88
–8
12
–12
LVCMOS18(3)
2
–2
0.4
VCCO 0.4
44
–4
66
–6
88
–8
LVCMOS15(3)
2
–2
0.4
VCCO 0.4
44
–4
66
–6
LVCMOS12(3)
22
–2
0.4
VCCO - 0.4
PCI33_3(4)
1.5
–0.5
10% VCCO
90% VCCO
HSTL_I_18
8
–8
0.4
VCCO - 0.4
HSTL_III_18
24
–8
0.4
VCCO - 0.4
SSTL18_I
6.7
–6.7
VTT – 0.475
VTT + 0.475
SSTL2_I
8.1
–8.1
VTT – 0.61
VTT + 0.61
Notes:
1.
The numbers in this table are based on the conditions set forth in
2.
Descriptions of the symbols used in this table are as follows:
IOL the output current condition under which VOL is tested
IOH the output current condition under which VOH is tested
VOL the output voltage that indicates a Low logic level
VOH the output voltage that indicates a High logic level
VCCO the supply voltage for output drivers
VTT the voltage applied to a resistor termination
3.
For the LVCMOS and LVTTL standards: the same VOL and VOH
limits apply for both the Fast and Slow slew attributes.
4.
Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/pci.
Table 10: DC Characteristics of User I/Os Using
Single-Ended Standards (Continued)
IOSTANDARD
Attribute
Test
Conditions
Logic Level
Characteristics
IOL
(mA)
IOH
(mA)
VOL
Max (V)
VOH
Min (V)
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