参数资料
型号: XC2S100-5FG256C
厂商: Xilinx Inc
文件页数: 62/99页
文件大小: 0K
描述: IC FPGA 2.5V 600 CLB'S 256-FBGA
标准包装: 1
系列: Spartan®-II
LAB/CLB数: 600
逻辑元件/单元数: 2700
RAM 位总计: 40960
输入/输出数: 176
门数: 100000
电源电压: 2.375 V ~ 2.625 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 256-BGA
供应商设备封装: 256-FBGA(17x17)
其它名称: 122-1226
XC2S100-5FG256C-ND
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
65
R
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Symbol
Description
Speed Grade
Units
-6
-5
Min
Max
Min
Max
Combinatorial Delays
TOPX
F operand inputs to X via XOR
-
0.8
-
0.9
ns
TOPXB
F operand input to XB output
-
1.3
-
1.5
ns
TOPY
F operand input to Y via XOR
-
1.7
-
2.0
ns
TOPYB
F operand input to YB output
-
1.7
-
2.0
ns
TOPCYF
F operand input to COUT output
-
1.3
-
1.5
ns
TOPGY
G operand inputs to Y via XOR
-
0.9
-
1.1
ns
TOPGYB
G operand input to YB output
-
1.6
-
2.0
ns
TOPCYG
G operand input to COUT output
-
1.2
-
1.4
ns
TBXCY
BX initialization input to COUT
-
0.9
-
1.0
ns
TCINX
CIN input to X output via XOR
-
0.4
-
0.5
ns
TCINXB
CIN input to XB
-
0.1
-
0.1
ns
TCINY
CIN input to Y via XOR
-
0.5
-
0.6
ns
TCINYB
CIN input to YB
-
0.6
-
0.7
ns
TBYP
CIN input to COUT output
-
0.1
-
0.1
ns
Multiplier Operation
TFANDXB
F1/2 operand inputs to XB output via AND
-
0.5
-
0.5
ns
TFANDYB
F1/2 operand inputs to YB output via AND
-
0.9
-
1.1
ns
TFANDCY
F1/2 operand inputs to COUT output via AND
-
0.5
-
0.6
ns
TGANDYB
G1/2 operand inputs to YB output via AND
-
0.6
-
0.7
ns
TGANDCY
G1/2 operand inputs to COUT output via AND
-
0.2
-
0.2
ns
Setup/Hold Times with Respect to Clock CLK(1)
TCCKX / TCKCX
CIN input to FFX
1.1 / 0
-
1.2 / 0
-
ns
TCCKY / TCKCY
CIN input to FFY
1.2 / 0
-
1.3 / 0
-
ns
Notes:
1.
A zero hold time listing indicates no hold time or a negative hold time.
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