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参数资料
| 型号： | XC3020A7PC68I |
| 厂商： | Xilinx, Inc. |
| 英文描述： | IC-SMD-FPGA |
| 中文描述： | 集成电路贴片的FPGA |
| 文件页数： | 45/76页 |
| 文件大小： | 731K |
| 代理商： | XC3020A7PC68I |
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R
November 9, 1998 (Version 3.1)
7-7
XC3000 Series Field Programmable Gate Arrays
7
The memory cell outputs Q and Q use ground and VCC lev-
els and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing infor-
mation, embedded in the program data by the development
system, to direct memory-cell loading. The serial-data
framing and length-count preamble provide programming
compatibility for mixes of various FPGA device devices in a
synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB shown in Figure 4, provides an
interface between the external package pin of the device
and the internal user logic. Each IOB includes both regis-
tered and direct input paths. Each IOB provides a program-
mable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each IOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.
Q
Data
Read or
Write
Configuration
Control
Q
X5382
Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and con-
trols one program selection in the Field Programmable
Gate Array.
FLIP
FLOP
Q
D
R
SLEW
RATE
PASSIVE
PULL UP
OUTPUT
SELECT
3-STATE
INVERT
OUT
INVERT
FLIP
FLOP
or
LATCH
D
Q
R
REGISTERED IN
DIRECT IN
OUT
3- STATE
(OUTPUT ENABLE)
TTL or
CMOS
INPUT
THRESHOLD
OUTPUT
BUFFER
(GLOBAL RESET)
CK1
X3029
I/O PAD
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
PROGRAMMABLE INTERCONNECTION POINT or PIP
=
IK
OK
Q
I
O
T
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
Figure 4: Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.
A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC3020A-7PC68I | 制造商:XILINX 制造商全称:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3020A-7PC84C | 功能描述:IC LOGIC CL ARRAY 2000GAT 84PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC3000A/L 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC3020A-7PC84C0100 | 制造商:Xilinx 功能描述: |
| XC3020A-7PC84I | 制造商:Xilinx 功能描述: |
| XC3020A-7PCG68C | 制造商:Xilinx 功能描述: |
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