参数资料
| 型号： | XC4006E-4TQ144I |
| 厂商： | Xilinx Inc |
| 文件页数： | 56/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA I-TEMP 5V 4SPD 144-TQFP |
| 产品变化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 标准包装： | 60 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 256 |
| 逻辑元件/单元数： | 608 |
| RAM 位总计： | 8192 |
| 输入/输出数： | 113 |
| 门数： | 6000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-10
May 14, 1999 (Version 1.6)
Flip-Flops
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two ip-ops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type ip-ops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in Table 2.
Latches (XC4000X only)
The CLB storage elements can also be congured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs. Storage element functionality is
described in Table 2.
Clock Input
Each ip-op can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
Clock Enable
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
LOGIC
FUNCTION
OF
G1-G4
G4
G3
G2
G1
G'
LOGIC
FUNCTION
OF
F1-F4
F4
F3
F2
F1
F'
LOGIC
FUNCTION
OF
F', G',
AND
H1
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
G'
H'
F'
S/R
CONTROL
D
EC
RD
Bypass
SD
YQ
XQ
Q
S/R
CONTROL
D
EC
RD
SD
Q
1
K
(CLOCK)
Multiplexer Controlled
by Configuration Program
Y
X
DIN/H2
H1
SR/H0
EC
X6692
C1 C4
4
Figure 1: Simplied Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
Table 2: CLB Storage Element Functionality
(active rising edge is shown)
Mode
K
EC
SR
D
Q
Power-Up or
GSR
XXXX
SR
Flip-Flop
XX
1
X
SR
__/
1*
0*
D
0X
0*
X
Q
Latch
11*
0*
X
Q
01*
0*
D
Both
X
0
0*
X
Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
Product Obsolete or Under Obsolescence
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