参数资料
| 型号： | XC4006E-4TQ144I |
| 厂商： | Xilinx Inc |
| 文件页数： | 57/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA I-TEMP 5V 4SPD 144-TQFP |
| 产品变化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 标准包装： | 60 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 256 |
| 逻辑元件/单元数： | 608 |
| RAM 位总计： | 8192 |
| 输入/输出数： | 113 |
| 门数： | 6000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-64
May 14, 1999 (Version 1.6)
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The rst byte of parallel congura-
tion data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con-
secutive rising CCLK edge.
The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
The lead FPGA serializes the data and presents the pre-
amble data (and all data that overows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK peri-
ods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each
daisy-chained device.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, M0).
X9027
CONTROL
SIGNALS
DATA BUS
PROGRAM
DOUT
M0 M1
M2
D0-7
INIT
DONE
PROGRAM
4.7 k
4.7 k
4.7 k
RDY/BUSY
VCC
OPTIONAL
DAISY-CHAINED
FPGAs
NOTE:
M2 can be shorted to Ground
if not used as I/O
CCLK
CLOCK
PROGRAM
DOUT
XC4000E/X
SLAVE
XC4000E/X
SYNCHRO-
NOUS
PERIPHERAL
M0 M1
N/C
8
M2
DIN
INIT
DONE
CCLK
N/C
Figure 56: Synchronous Peripheral Mode Circuit Diagram
Product Obsolete or Under Obsolescence
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