参数资料
| 型号： | XC4013E-4PQ240I |
| 厂商： | Xilinx Inc |
| 文件页数： | 3/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA I-TEMP 5V 4SPD 240-PQFP |
| 产品变化通告： | Product Discontinuation 28/Jul/2010 |
| 标准包装： | 24 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 576 |
| 逻辑元件/单元数： | 1368 |
| RAM 位总计： | 18432 |
| 输入/输出数： | 192 |
| 门数： | 13000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 240-BFQFP |
| 供应商设备封装： | 240-PQFP（32x32） |
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R
May 14, 1999 (Version 1.6)
6-15
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Dual-Port Edge-Triggered Mode
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
port and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
Dual-port mode always has edge-triggered write timing, as
shown in Figure 3.
Figure 6 shows a simple model of an XC4000 Series CLB
congured as dual-port RAM. One address port, labeled
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM array. The
RAM output, Single Port Out (SPO), appears at the F func-
tion generator output. SPO, therefore, reects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the G function
generator. The write address for the G function generator,
however, comes from the address A[3:0]. The output from
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reects the
data at address DPRA[3:0].
Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effec-
tive throughput of the FIFO.
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table 6. See Figure 7 on page 16 for a block diagram of a
CLB congured in this mode.
Table 6: Dual-Port Edge-Triggered RAM Signals
Note: The pulse following the active edge of WCLK (TWPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
gured as edge-triggered RAM.
Single-Port Level-Sensitive Timing Mode
Note: Edge-triggered mode is recommended for all new
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000 Series backward-com-
patibility with the XC4000 family.
Level-sensitive RAM timing is simple in concept but can be
complicated in execution. Data and address signals are
presented, then a positive pulse on the write enable pin
(WE) performs a write into the RAM at the designated
address. As indicated by the “level-sensitive” label, this
RAM acts like a latch. During the WE High pulse, changing
the data lines results in new data written to the old address.
Changing the address lines while WE is High results in spu-
rious data written to the new address—and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
The user must generate a carefully timed WE signal. The
delay on the WE signal and the address lines must be care-
fully veried to ensure that WE does not become active
until after the address lines have settled, and that WE goes
inactive before the address lines change again. The data
must be stable before and after the falling edge of WE.
In practical terms, WE is usually generated by a 2X clock. If
a 2X clock is not available, the falling edge of the system
clock can be used. However, there are inherent risks in this
approach, since the WE pulse must be guaranteed inactive
before the next rising edge of the system clock. Several
older application notes are available from Xilinx that dis-
cuss the design of level-sensitive RAMs.
However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
WE
DD
Q
DQ
D
DPRA[3:0]
A[3:0]
AR[3:0]
AW[3:0]
WE
D
AR[3:0]
AW[3:0]
RAM16X1D Primitive
F Function Generator
G Function Generator
DPO (Dual Port Out)
Registered DPO
SPO (Single Port Out)
Registered SPO
WCLK
X6755
Figure 6: XC4000 Series Dual-Port RAM, Simple
Model
RAM Signal
CLB Pin
Function
D
D0
Data In
A[3:0]
F1-F4
Read Address for F,
Write Address for F and G
DPRA[3:0]
G1-G4
Read Address for G
WE
Write Enable
WCLK
K
Clock
SPO
F’
Single Port Out
(addressed by A[3:0])
DPO
G’
Dual Port Out
(addressed by DPRA[3:0])
Product Obsolete or Under Obsolescence
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4013E-4PQ240M | 制造商:XILINX 制造商全称:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-4TQ240C | 制造商:XILINX 制造商全称:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-4TQ240I | 制造商:XILINX 制造商全称:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-4TQ240M | 制造商:XILINX 制造商全称:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-4VQ240C | 制造商:XILINX 制造商全称:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
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