参数资料
型号: XC4013E-4PQ240I
厂商: Xilinx Inc
文件页数: 55/68页
文件大小: 0K
描述: IC FPGA I-TEMP 5V 4SPD 240-PQFP
产品变化通告: Product Discontinuation 28/Jul/2010
标准包装: 24
系列: XC4000E/X
LAB/CLB数: 576
逻辑元件/单元数: 1368
RAM 位总计: 18432
输入/输出数: 192
门数: 13000
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 240-BFQFP
供应商设备封装: 240-PQFP(32x32)
R
May 14, 1999 (Version 1.6)
6-63
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Figure 55: Master Parallel Mode Programming Switching Characteristics
Address for Byte n
Byte
2 TDRC
Address for Byte n + 1
D7
D6
A0-A17
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
1 TRAC
7 CCLKs
CCLK
3 TRCD
Byte n - 1
X6078
Description
Symbol
Min
Max
Units
RCLK
Delay to Address valid
1
TRAC
0
200
ns
Data setup time
2
TDRC
60
ns
Data hold time
3
TRCD
0ns
Notes:
1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conguration by pulling PROGRAM
Low until Vcc is valid.
2. The rst Data byte is loaded and CCLK starts at the end of the rst RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Product Obsolete or Under Obsolescence
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