参数资料
| 型号： | XC4020XL-3PQ240I |
| 厂商： | Xilinx Inc |
| 文件页数： | 18/68页 |
| 文件大小： | 0K |
| 描述： | IC FPGA I-TEMP 3.3V 3SPD 240PQFP |
| 产品变化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 标准包装： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB数： | 784 |
| 逻辑元件/单元数： | 1862 |
| RAM 位总计： | 25088 |
| 输入/输出数： | 192 |
| 门数： | 20000 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 240-BFQFP |
| 供应商设备封装： | 240-PQFP（32x32） |
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R
May 14, 1999 (Version 1.6)
6-29
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Table 14: Routing per CLB in XC4000 Series Devices
Programmable Switch Matrices
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each switch matrix consists of programmable pass
transistors used to establish connections between the lines
(see Figure 26).
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a dou-
ble-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
Single-Length Lines
Single-length lines provide the greatest interconnect exi-
bility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switch-
ing matrices that are located in every row and a column of
CLBs.
Single-length lines are connected by way of the program-
mable switch matrices, as shown in Figure 28. Routing
connectivity is shown in Figure 27.
Single-length lines incur a delay whenever they go through
a switching matrix. Therefore, they are not suitable for rout-
ing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
branching for nets with fanout greater than one.
x5994
Quad
Single
Double
Long
Direct
Connect
Long
CLB
Long
Global
Clock
Long
Double Single
Global
Clock
Carry
Chain
Direct
Connect
Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)
XC4000E
XC4000X
Vertical Horizontal Vertical Horizontal
Singles
8
Doubles
4
Quads
0
12
Longlines
6
10
6
Direct
Connects
00
2
Globals
4
0
8
0
Carry Logic
2
0
1
0
Total
24
18
45
32
Six Pass Transistors
Per Switch Matrix
Interconnect Point
Singles
Double
Singles
Double
X6600
Figure 26: Programmable Switch Matrix (PSM)
Product Obsolete or Under Obsolescence
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