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参数资料
| 型号： | XC4025E-4PGG299M |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1024 CLBS, 15000 GATES, 111 MHz, CPGA299 |
| 封装： | CERAMIC, PGA-299 |
| 文件页数： | 17/23页 |
| 文件大小： | 138K |
| 代理商： | XC4025E-4PGG299M |
November 21, 1997 (Version 1.3)
8-13
XC4000E DC Characteristics Over Operating Conditions
Note 1:
With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
Note 2:
With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
congured with the development system Tie option.
*
Characterized Only.
XC4000E Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB ip-ops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature)
Symbol
Description
Min
Max
Units
VOH
High-level output voltage @ IOH = -4.0mA, VCC min
TTL outputs
2.4
V
VOL
Low-level output voltage @ IOL = 12.0mA, VCC min (Note 1) TTL outputs
0.4
V
ICCO
Quiescent FPGA supply current (Note 2)
50
mA
IL
Input or output leakage current
-10
+10
A
CIN
Input capacitance (sample tested)
16
pF
IRIN*
Pad pull-up (when selected) @ VIN = 0V (sample tested)
-0.02
-0.25
mA
IRLL*
Horizontal Longline pull-up (when selected) @ logic Low
0.2
2.5
mA
Speed Grade
-4
Units
Description
Symbol
Device
Max
From pad through
Primary buffer,
to any clock K
TPG
XC4005E
XC4010E
XC4013E
XC4025E
7.0
11.0
11.5
12.5
ns
From pad through
Secondary buffer,
to any clock K
TSG
XC4005E
XC4010E
XC4013E
XC4025E
7.5
11.5
12.0
13.0
ns
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