- 您现在的位置：买卖IC网 > PDF目录205934 > XC4025E-4PGG299M (XILINX INC) FPGA, 1024 CLBS, 15000 GATES, 111 MHz, CPGA299 PDF资料下载
参数资料
| 型号： | XC4025E-4PGG299M |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1024 CLBS, 15000 GATES, 111 MHz, CPGA299 |
| 封装： | CERAMIC, PGA-299 |
| 文件页数： | 4/23页 |
| 文件大小： | 138K |
| 代理商： | XC4025E-4PGG299M |
XC4000E High-Reliability Field Programmable Gate Arrays
8-22
November 21, 1997 (Version 1.3)
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data,
reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Speed Grade
-4
Units
Description
Symbol
Device
Global Clock to Output
(fast) using OFF
TICKOF
(Max)
XC4005E
XC4010E
XC4013E
XC4025E
14.0
16.0
16.5
17.0
ns
Global Clock to Output
(slew-limited) using OFF
TICKO
(Max)
XC4005E
XC4010E
XC4013E
XC4025E
18.0
20.0
20.5
21.0
ns
Input Setup Time, using IFF
(no delay)
TPSUF
(Min)
XC4005E
XC4010E
XC4013E
XC4025E
2.0
1.9
1.6
1.5
ns
Input Hold Time, using IFF
(no delay)
TPHF
(Min)
XC4005E
XC4010E
XC4013E
XC4025E
4.6
6.0
7.0
8.0
ns
Input Setup Time, using IFF
(with delay)
TPSU
(Min)
XC4005E
XC4010E
XC4013E
XC4025E
8.5
9.5
ns
Input Hold Time, using IFF
(with delay)
TPH
(Min)
XC4005E
XC4010E
XC4013E
XC4025E
0
ns
OFF = Output Flip-Flop
IFF = Input Flip-Flop or Latch
OFF
Global Clock-to-Output Delay
.
X3202
TPG
OFF
Global Clock-to-Output Delay
.
X3202
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
TPG
相关PDF资料 |
PDF描述 |
|---|---|
| XC5204-3PQ240C | Field Programmable Gate Arrays |
| XC5204-3TQ176C | Field Programmable Gate Arrays |
| XC5204-3VQ64C | Field Programmable Gate Arrays |
| XC5204-4BG225C | Field Programmable Gate Arrays |
| XC5204-4BG352C | Field Programmable Gate Arrays |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4028EX-2HQ208C | 功能描述:IC FPGA 1024 CLB'S 208-HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC4028EX-2HQ240C | 制造商:Xilinx 功能描述: |
| XC4028EX-3HQ208C | 功能描述:IC FPGA 1024 CLB'S 208-HQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC4000E/X 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC4028EX-3HQ208I | 制造商:Xilinx 功能描述: |
| XC4028EX-3HQ240C | 制造商:Xilinx 功能描述: |
发布紧急采购，3分钟左右您将得到回复。