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参数资料
| 型号： | XC4025E-4PGG299M |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1024 CLBS, 15000 GATES, 111 MHz, CPGA299 |
| 封装： | CERAMIC, PGA-299 |
| 文件页数： | 7/23页 |
| 文件大小： | 138K |
| 代理商： | XC4025E-4PGG299M |
November 21, 1997 (Version 1.3)
8-25
XC4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
Note 1:
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 2:
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-
up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.
Speed Grade
-4
Units
Description
Symbol
Min
Max
Propagation Delays (TTL Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (O) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited
TOKPOF
TOKPOS
TOPF
TOPS
TTSHZ
TTSONF
TTSONS
7.5
11.5
8.0
12.0
10.0
13.7
ns
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