参数资料
型号: XC4025E-4PGG299M
厂商: XILINX INC
元件分类: FPGA
英文描述: FPGA, 1024 CLBS, 15000 GATES, 111 MHz, CPGA299
封装: CERAMIC, PGA-299
文件页数: 5/23页
文件大小: 138K
代理商: XC4025E-4PGG299M
November 21, 1997 (Version 1.3)
8-23
XC4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data,
reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Note 1:
Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2:
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-
up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.
Speed Grade
-4
Units
Description
Symbol
Device
Min
Max
Propagation Delays (TTL Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent latch, no delay
with delay
TPID
TPLI
TPDLI
All devices
XC4005E
XC4010E
XC4013E
XC4025E
3.0
6.0
12.0
12.2
12.6
15.0
ns
Propagation Delays
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
TIKRI
TIKLI
All devices
6.8
7.3
ns
Hold Times (Note 1)
Pad to Clock (IK), no delay
with delay
TIKPI
TIKPID
All devices
0
ns
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