参数资料
型号: XC4VFX100-11FF1152I
厂商: XILINX INC
元件分类: FPGA
英文描述: FPGA, 10544 CLBS, 1181 MHz, PBGA1152
封装: FBGA-1152
文件页数: 53/58页
文件大小: 1863K
代理商: XC4VFX100-11FF1152I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
57
09/28/07
3.0
SPEED SPECIFICATION version for this data sheet release: v1.67.
Promoted data sheet to Production status.
Table 14: Moved XC4VFX140, all speed grades, from Advance to Production status.
Table 59: Added/updated all Global Clock Tree Skew values. Qualified Note (2) by
adding “vertical”.
Table 60: Added Package Skew values for XC4VFX40, XC4VFX100, and XC4VFX140.
Table 63: Added JTAG ID code for XC4VFX140.
12/11/07
3.1
SPEED SPECIFICATION version for this data sheet release: v1.68.
Added new copyright notice and legal disclaimer section.
Table 13: Removed table note references to XAPP700, XAPP704, and XAPP705
(obsolete). Renumbered table notes.
Table 15: Added new Note 1, renumbered subsequent table notes.
Table 30: Removed table rows for LVPECL_33, LVDS_33, and LVDSEXT_33.
Table 30, Table 31: Corrected “electron-coupled” to “emitter-coupled”.
Table 31: For LVDS Extended Mode 2.5V, corrected I/O Standard Attribute to
LVDSEXT_25.
Table 37: Added Note 4 specifying FTOG for -11 FX devices as 1181 MHz.
Table 43: Added parameter FMAX_READBACK.
Table 58: Corrected TPSFD for XC4VFX100 devices to 1.99 ns.
Section Production Stepping, page 51: Advised that current stepping level is reported
by the ISE tool in the PAR report.
04/10/08
3.2
SPEED SPECIFICATION version for this data sheet release: v1.68.
Table 28, page 22: Re-inserted table.
Table 43, page 36: Updated Symbol names for the DRP entries.
Table 63, page 51: Revised code for XC4VFX40 package to 0.
06/06/08
3.3
SPEED SPECIFICATION version for this data sheet release: v1.68.
Table 3, page 3: In Note (2), clarified differences between settings for typical and
maximum ICC numbers.
Table 24, page 16: Revised FGCLK to show different maximum frequencies depending
on the speed grade. Removed TPHASE.
Table 35, page 29: Reorganized according to IDELAYCTRL and IDELAY.
11/26/08
3.4
Table 35, page 29: Added FMAX.
06/16/09
3.5
Table 40, page 33: Changed TRCKO_DOA to a Max parameter.
08/13/09
3.6
Table 3, page 3: Updated Note 1.
Table 45, page 38: Added Note 6 reference to and updated descriptions of
CLKIN_FREQ_DLL_HF_MS_MIN and CLKIN_FREQ_FX_HF_MS_MAX.
09/09/09
3.7
Table 7, page 8: Added “LVCMOS” to Notes 3 and 4.
Date
Version
Revisions
相关PDF资料
PDF描述
XC4VFX100-11FF1517I FPGA, 10544 CLBS, 1181 MHz, PBGA1517
XC4VFX100-10FFG1152I FPGA, 10544 CLBS, 1028 MHz, PBGA1152
XC4VFX100-10FFG1517I FPGA, 10544 CLBS, 1028 MHz, PBGA1517
XC4VFX100-11FFG1152I FPGA, 10544 CLBS, 1181 MHz, PBGA1152
XC4VFX100-11FFG1517I FPGA, 10544 CLBS, 1181 MHz, PBGA1517
相关代理商/技术参数
参数描述
XC4VFX100-11FF1517C 制造商:Xilinx 功能描述:FPGA VIRTEX-4 94896 CELLS 90NM 1.2V 1517FCBGA - Trays
XC4VFX100-11FF1517CES4 制造商:Xilinx 功能描述:
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XC4VFX100-11FF1517IES4 制造商:Xilinx 功能描述: