参数资料
型号: XC6SLX75T-3FG676I
厂商: Xilinx Inc
文件页数: 7/89页
文件大小: 0K
描述: IC FPGA SPARTAN 6 676FGGBGA
标准包装: 40
系列: Spartan® 6 LXT
LAB/CLB数: 5831
逻辑元件/单元数: 74637
RAM 位总计: 3170304
输入/输出数: 348
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 676-BGA
供应商设备封装: 676-FBGA(27x27)
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
15
GTP Transceiver Switching Characteristics
Consult UG386: Spartan-6 FPGA GTP Transceivers User Guide for further information.
Table 17: GTP Transceiver Clock DC Input Level Specification
Symbol
DC Parameter
Min
Typ
Max
Units
VIDIFF
Differential peak-to-peak input voltage
200
800
2000
mV
RIN
Differential input resistance
80
100
120
CEXT
Required external AC coupling capacitor
100
nF
Table 18: GTP Transceiver Performance
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
FGTPMAX
Maximum GTP transceiver data rate
3.2
2.7
N/A
Gb/s
FGTPRANGE1
GTP transceiver data rate range when
PLL_TXDIVSEL_OUT = 1
1.88 to 3.2
1.88 to 2.7
N/A
Gb/s
FGTPRANGE2
GTP transceiver data rate range when
PLL_TXDIVSEL_OUT = 2
0.94 to 1.62
N/A
Gb/s
FGTPRANGE3
GTP transceiver data rate range when
PLL_TXDIVSEL_OUT = 4
0.6 to 0.81
N/A
Gb/s
FGPLLMAX
Maximum PLL frequency
1.62
N/A
GHz
FGPLLMIN
Minimum PLL frequency
0.94
N/A
GHz
Table 19: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
FGTPDRPCLK
GTP transceiver DCLK (DRP clock) maximum frequency
125
100
N/A
MHz
Table 20: GTP Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
All LXT Speed Grades
Units
Min
Typ
Max
FGCLK
Reference clock frequency range
60
160
MHz
TRCLK
Reference clock rise time
20% – 80%
200
ps
TFCLK
Reference clock fall time
80% – 20%
200
ps
TDCREF
Reference clock duty cycle
Transceiver PLL only
45
50
55
%
TLOCK
Clock recovery frequency acquisition
time
Initial PLL lock
1
ms
TPHASE
Clock recovery phase acquisition time Lock to data after PLL has locked to
the reference clock
––
200
s
X-Ref Target - Figure 3
Figure 3: Reference Clock Timing Parameters
ds162_05_042109
80%
20%
TFCLK
TRCLK
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