参数资料
| 型号： | XCS10-3VQ100I |
| 厂商： | Xilinx Inc |
| 文件页数： | 26/83页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 5V I-TEMP 100-VQFP |
| 产品变化通告： | Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 |
| 标准包装： | 90 |
| 系列： | Spartan® |
| LAB/CLB数： | 196 |
| 逻辑元件/单元数： | 466 |
| RAM 位总计： | 6272 |
| 输入/输出数： | 77 |
| 门数： | 10000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-VQFP（14x14） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页
Spartan and Spartan-XL FPGA Families Data Sheet
32
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Legend:
A selection of CRC or non-CRC error checking is allowed by
the bitstream generation software. The Spartan-XL family
Express mode only supports non-CRC error checking. The
non-CRC
error
checking
tests
for
a
designated
end-of-frame field for each frame. For CRC error checking,
the software calculates a running CRC and inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an FPGA includes the last
seven data bits.
Detection of an error results in the suspension of data load-
ing before DONE goes High, and the pulling down of the
INIT pin. In Master serial mode, CCLK continues to operate
externally. The user must detect INIT and initialize a new
configuration by pulsing the PROGRAM pin Low or cycling
VCC.
Cyclic Redundancy Check (CRC) for Configura-
tion and Readback
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 16. If a frame data
error is detected during the loading of the FPGA, the config-
uration process with a potentially corrupted bitstream is ter-
minated. The FPGA pulls the INIT pin Low and goes into a
Wait state.
Table 16: Spartan/XL Data Stream Formats
Data Type
Serial Modes
(D0...)
Express Mode
(D0-D7)
(Spartan-XL only)
Fill Byte
11111111b
FFFFh
Preamble Code
0010b
11110010b
Length Count
COUNT[23:0]
COUNT[23:0](1)
Fill Bits
1111b
-
Field Check
Code
-
11010010b
Start Field
0b
11111110b(2)
Data Frame
DATA[n–1:0]
CRC or Constant
Field Check
xxxx (CRC)
or 0110b
11010010b
Extend Write
Cycle
-
FFD2FFFFFFh
Postamble
01111111b
-
Start-Up Bytes(3)
FFh
FFFFFFFFFFFFFFh
Unshaded
Once per bitstream
Light
Once per data frame
Dark
Once per device
Notes:
1.
Not used by configuration logic.
2.
11111111b for XCS40XL only.
3.
Development system may add more start-up bytes.
相关PDF资料 |
PDF描述 |
|---|---|
| XCS10-3VQ100C | IC FPGA 5V C-TEMP 100-VQFP |
| XCS10-3TQ144C | IC FPGA 5V C-TEMP 144-TQFP |
| XCS10-3PC84C | IC FPGA 5V C-TEMP 84-PLCC |
| XCS05XL-5VQ100C | IC FPGA 3.3V C-TEMP 100-VQFP |
| XCS05XL-5PC84C | IC FPGA 3.3V C-TEMP 84-PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XCS10-3VQ144C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10-3VQ144I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10-3VQ208C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10-3VQ208I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10-3VQ240C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
发布紧急采购，3分钟左右您将得到回复。