参数资料
| 型号： | XOCLCC6EVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/9页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XOCLCC6 |
| 设计资源： | XOCLCC6EVB Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟振荡器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | NBXxxxx 时钟振荡器，6-CLCC 封装 |
| 主要属性： | 用于 6-CLCC NBXxxxx 振荡器的衬垫 |
| 次要属性： | 单电源或分离式电源 |
| 已供物品： | 板 |
| 其它名称： | XOCLCC6EVBOS |
XOCLCC6EVB
LVDS : Driver termination is a 100 W resistor across the
differential lines located at the receiver input.
Step 3: Configure FSEL and OE
The FSEL and OE control pins can be controlled from an
external source via the appropriate test point, or via the
Table 4. TYPICAL LAB SETUP
LOGIC Levels Power Supply
Typical Lab
Setup
jumper headers located on the evaluation board, as indicated
in Figures 2 and 7. Refer to the specific device datasheet for
details on the proper settings for these pins.
LVPECL
CML
LVDS
Split 3.3 V
Single ? 3.3 V
Single 3.3 V
See Figure 4
See Figure 5
See Figure 6
+2.0V
Digital Oscilloscope
Or Frequency Counter
VDD = +2.0V
H
L
VDD
+
+2.0V
?
OE
J1
Power Supply
H
L
50 W
+
FSEL
J2
+1.3V
?
SMAGND
C3
50 W
DUTGND
C4
VEE = ? 1.3
? 1.3
0V
Figure 4. Split Power Supply Lab Setup for LVPECL Outputs (DO NOT JUMPER DUTGND and SMAGND)
http://onsemi.com
4
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