参数资料
| 型号： | XR16C2850IM-F |
| 厂商： | Exar Corporation |
| 文件页数： | 17/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 128B DUAL 48TQFP |
| 标准包装： | 250 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 128 字节 |
| 规程： | RS232，RS485 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
| 其它名称： | 1016-1275 |
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XR16C2850
xr
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
REV. 2.1.3
24
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16C2850 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bits 1-4 generate an interrupt immediately when
the character has been received.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode section for complete details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from LOW to HIGH.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16C2850IMTR-F | 制造商:Exar Corporation 功能描述:XR16C2850IMTR-F |
| XR16C2850IP | 制造商:EXAR 制造商全称:EXAR 功能描述:DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2850IP40 | 制造商:EXAR 制造商全称:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2852 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
| XR16C2852_05 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
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