参数资料
| 型号： | XR16C2850IM-F |
| 厂商： | Exar Corporation |
| 文件页数： | 23/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 128B DUAL 48TQFP |
| 标准包装： | 250 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 128 字节 |
| 规程： | RS232，RS485 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
| 其它名称： | 1016-1275 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页
xr
XR16C2850
REV. 2.1.3
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
3
PIN DESCRIPTIONS
NAME
44-PLCC
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
29
30
31
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
I/O
Data bus lines [7:0] (bidirectional).
IOR#
24
19
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
20
15
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
16
10
I
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
CSB#
17
11
I
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
INTA
33
30
O
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output is LOW when MCR[3] is set to a logic 1. INTA
is set to the three state mode and OP2A# is HIGH when MCR[3] is set
to a logic 0 (default). See MCR[3]. If this output is not used, leave it
unconnected.
INTB
32
29
O
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output is LOW when MCR[3] is set to a logic 1. INTB
is set to the three state mode and OP2B# is HIGH when MCR[3] is set
to a logic 0 (default). See MCR[3]. If this output is not used, leave it
unconnected.
TXRDYA#
1
43
O
UART channel A Transmitter Ready (active low). The output
provides the TX FIFO/THR status for transmit channel A. See
Table 2. If this output is not used, leave it unconnected.
RXRDYA#
34
31
O
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
Table 2. If this output
is not used, leave it unconnected.
TXRDYB#
12
6
O
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 2. If this
output is not used, leave it unconnected.
相关PDF资料 |
PDF描述 |
|---|---|
| XR16C2852IJ-F | IC UART FIFO 128B 44PLCC |
| XR16C850IMTR-F | IC UART FIFO 128B 48TQFP |
| XR16C854IQ-F | IC UART FIFO 128B QUAD 100QFP |
| XR16C864IQ-F | IC UART FIFO 128B QUAD 100QFP |
| XR16L2450IJ-F | IC UART FIFO 1B DUAL 44PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16C2850IMTR-F | 制造商:Exar Corporation 功能描述:XR16C2850IMTR-F |
| XR16C2850IP | 制造商:EXAR 制造商全称:EXAR 功能描述:DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2850IP40 | 制造商:EXAR 制造商全称:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2852 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
| XR16C2852_05 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
发布紧急采购，3分钟左右您将得到回复。