参数资料
| 型号： | XR16C2850IM-F |
| 厂商： | Exar Corporation |
| 文件页数： | 2/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 128B DUAL 48TQFP |
| 标准包装： | 250 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 128 字节 |
| 规程： | RS232，RS485 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
| 其它名称： | 1016-1275 |
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XR16C2850
xr
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
REV. 2.1.3
10
2.7
INTA and INTB Ouputs
The INTA and INTB interrupt output output changes according to the operating mode and enahnced features
setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figures 20
through 25.
2.8
Crystal Oscillator or External Clock Input
The 2850 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. SEE”PROGRAMMABLE BAUD
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4). Alternatively, an external
clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin
NO
LOW = a byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
INTA/B Pin
YES
LOW = a byte in THR
HIGH = transmitter empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or transmitter empty
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
C1
22-47 pF
C2
22-47 pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500Κ1Μ
XTAL1
XTAL2
相关PDF资料 |
PDF描述 |
|---|---|
| XR16C2852IJ-F | IC UART FIFO 128B 44PLCC |
| XR16C850IMTR-F | IC UART FIFO 128B 48TQFP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16C2850IMTR-F | 制造商:Exar Corporation 功能描述:XR16C2850IMTR-F |
| XR16C2850IP | 制造商:EXAR 制造商全称:EXAR 功能描述:DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2850IP40 | 制造商:EXAR 制造商全称:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2852 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
| XR16C2852_05 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
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