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参数资料
| 型号： | XR16C850CJ-F |
| 厂商： | Exar Corporation |
| 文件页数： | 4/56页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 128B 44PLCC |
| 标准包装： | 27 |
| 特点： | * |
| 通道数： | 1，UART |
| FIFO's： | 128 字节 |
| 规程： | RS485 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 管件 |
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XR16C850
xr
2.97V TO 5.5V UART WITH 128-BYTE FIFO
REV. 2.3.1
12
2.7
Internal Registers
The 850 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard 16C550. These registers
function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control
register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scractchpad register
(SPR).
Beyond the general 16C550 features and capabilities, the 850 offers enhanced feature registers (EMSR, TRG,
FC, FCTR, EFR, Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, Xon/Xoff
software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger level control,
and FIFO level counters. All the register functions are discussed in full detail later in “Section 3.0, UART
2.8
DMA Mode
The DMA Mode (a legacy term) in this document does not mean “Direct Memory Access” but refers to data
block transfer operation. The DMA mode affects the state of the RXRDY# A/B and TXRDY# A/B output pins.
The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation.
The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data.
The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1). When the
transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 850 activates the
interrupt output pin for each data transmit or receive operation. When DMA mode is enabled (FCR bit-3 = 1),
the user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence
determined by the programmed trigger level. In this mode, the 850 sets the TXRDY# pin when the transmit
FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following table
shows their behavior.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B
0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B
0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16C850CJTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC T/R 制造商:Exar Corporation 功能描述:XR16C850CJTR-F |
| XR16C850CM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C850CM-0A-EVB | 功能描述:UART 接口集成电路 Supports C850 48 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16C850CM-F | 功能描述:UART 接口集成电路 UARTW/128BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16C850CMTR-F | 功能描述:UART 接口集成电路 UART w/128 Bytes FIFO & IrDA RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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