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参数资料
| 型号： | XR16M564IV-0A-EVB |
| 厂商： | Exar Corporation |
| 文件页数： | 28/55页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR16M564-A 64LQFP |
| 标准包装： | 1 |
| 系列： | * |
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XR16M564/564D
34
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.0
4.8
Line Status Register (LSR) - Read/Write
This register is writeable but it is not recommended. The LSR provides the status of data transfers between the
UART and the host. If IER bit-2 is enabled, LSR bit 1 will generate an interrupt immediately and LSR bits 2-4
will generate an interrupt when a character with an error is in the RHR.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Tag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or HIGH.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to HIGH when the last data byte is
transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently
with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the
transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to HIGH whenever the transmitter goes idle. It is set to LOW whenever either the THR or TSR
contains a data character. In the FIFO mode this bit is set to HIGH whenever the transmit FIFO and transmit
shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
Logic 0 = No FIFO error (default).
Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16M564IV-0B-EVB | 功能描述:界面开发工具 Eval Board for XR16M564IV-0B RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR16M564IV64 | 制造商:EXAR 制造商全称:EXAR 功能描述:1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO |
| XR16M564IV64-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16M564IV80 | 制造商:EXAR 制造商全称:EXAR 功能描述:1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO |
| XR16M564IV80-0A-EB | 功能描述:界面开发工具 Eval Board for XR16M564IV80-0A RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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