参数资料
型号: XR17C152IM-F
厂商: Exar Corporation
文件页数: 14/62页
文件大小: 0K
描述: IC UART PCI BUS DUAL 100TQFP
标准包装: 90
特点: *
通道数: 2,DUART
FIFO's: 64 字节
规程: RS485
电源电压: 5V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 100-TQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
á
XR17C152
REV. 1.2.0
5V PCI BUS DUAL UART
21
3.0
TRANSMIT AND RECEIVE DATA
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel in the device configuration register
set to ease programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it
increases the data transfer rate on the PCI bus. Additionally, a special register location provides receive data
byte with its associated error tags. This is a 16-bit or 32-bit read operation where the Line Status Register
(LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates
data unloading with the error tags without having to read the LSR register separately. Furthermore, the
XR17C152 supports PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error tags before reading the data
byte.
3.1
DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS
The XR17C152 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory
region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory
location (apart from the 16550 register set) where the RX and the TX FIFO can be read from/written to, as
shown in Table 2 on page 10. The following is an extract from the table showing the burstable memory
locations:
Channel 0:
RX FIFO
:
0x100 - 0x13F (64 bytes)
TX FIFO
:
0x100 - 0x13F (64 bytes)
RX FIFO + status
:
0x180 - 0x1FF (64 bytes data + 64 bytes status)
Channel 1:
RX FIFO
:
0x300 - 0x33F (64 bytes)
TX FIFO
:
0x300 - 0x33F (64 bytes)
RX FIFO + status
:
0x380 - 0x3FF (64 bytes data + 64 bytes status)
3.1.1
Normal Rx FIFO Data Unloading at locations 0x100 (channel 0) and 0x300 (channel 1)
The RX FIFO data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation
(maximum 16 DWORD reads) at memory locations 0x100 (channel 0) and 0x300 (channel 1). This operation is
at least 16 times faster than reading the data in 64 separate 8-bit memory reads of RHR register (0x000 for
channel 0 and 0x200 for channel 1).
READ RX FIFO,
WITH NO ERRORS
BYTE 3
BYTE 2BYTE 1BYTE 0
Read n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Read n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
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