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参数资料
型号： XR17C152IM-F
厂商： Exar Corporation
文件页数： 57/62页
文件大小： 0K
描述： IC UART PCI BUS DUAL 100TQFP
标准包装： 90
特点： *
通道数： 2，DUART
FIFO's： 64 字节
规程： RS485
电源电压： 5V
带自动流量控制功能： 是
带IrDA 编码器/解码器： 是
带故障启动位检测功能： 是
带调制解调器控制功能： 是
安装类型： 表面贴装
封装/外壳： 100-TQFP
供应商设备封装： 100-TQFP（14x14）
包装： 托盘
XR17C152
á
5V PCI BUS DUAL UART
REV. 1.2.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS .............................................................................................................................................1
FEATURES...................................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM ..................................................................................................................................................................... 1
FIGURE 2. PIN OUT OF THE DEVICE ......................................................................................................................................................... 2
ORDERING INFORMATION
..............................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
FUNCTIONAL DESCRIPTION ...........................................................................................6
PCI Local Bus Interface........................................................................................................................................ 6
PCI Local Bus Configuration Space Registers..................................................................................................... 6
EEPROM Interface ............................................................................................................................................... 6
1.0 XR17C152 Registers ............................................................................................................... 7
FIGURE 3. THE XR17C152 REGISTER SETS ............................................................................................................................................ 7
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................. 8
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ................................................................................................................ 8
1.2 DEVICE CONFIGURATION REGISTER SET ............................................................................................... 9
TABLE 2: XR17C152 DEVICE CONFIGURATION REGISTERS .................................................................................................................... 10
TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT........................................................................................... 10
TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT ...................................................................................... 11
1.2.1 The Interrupt Status Register ................................................................................................................... 12
FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3.......................................................................................... 13
TABLE 5: UART CHANNEL [1:0] INTERRUPT SOURCE ENCODING ............................................................................................................ 13
TABLE 6: UART CHANNEL [1:0] INTERRUPT CLEARING: .......................................................................................................................... 13
1.2.2 General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default 0xXX-XX-00-
00)
14
FIGURE 5. TIMER/COUNTER CIRCUIT. ..................................................................................................................................................... 14
TABLE 7: TIMER CONTROL REGISTERS .............................................................................................................................................. 14
1.2.3 8XMODE [7:0] (default 0x00) ................................................................................................................... 15
1.2.4 REGA [15:8] Reserved ............................................................................................................................. 15
1.2.5 RESET [23:16] - (default 0x00) ................................................................................................................ 15
1.2.6 SLEEP [31:24] - (default 0x00)................................................................................................................. 16
1.2.7 Device Identification and Revision............................................................................................................ 16
1.2.9 Multi-Purpose Inputs and Outputs ............................................................................................................ 17
1.2.10 MPIO REGISTER ................................................................................................................................... 17
1.2.8 REGB Register ......................................................................................................................................... 17
FIGURE 6. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT .................................................................................................................. 18
2.0 Crystal Oscillator / Buffer .................................................................................................... 20
FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS ...................................................................................................................................... 20
FIGURE 8. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE ................................................................................................. 20
3.0 Transmit and Receive Data ..................................................................................................21
3.1 DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS ................................. 21
3.1.1 Normal Rx FIFO Data Unloading at locations 0x100 (channel 0) and 0x300 (channel 1)....................... 21
3.1.2 Special Rx FIFO Data Unloading at locations 0x180 (channel 0) and 0x380 (channel 1) ...................... 22
3.1.3 Tx FIFO Data Loading at locations 0x100 (channel 0) and 0x300 (channel 1) ....................................... 22
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND
RHR IN 8-BIT FORMAT 24
4.0 UART ...................................................................................................................................... 24
4.1 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 24
TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE .................................................................... 24
FIGURE 9. BAUD RATE GENERATOR....................................................................................................................................................... 24
4.2 TRANSMITTER .................................................................................................................................... 25
4.2.1 Transmit Holding Register (THR) - Write-Only ......................................................................................... 25
4.2.2 Transmitter Operation in non-FIFO mode ................................................................................................ 25
TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................. 25
4.2.3 Transmitter Operation in FIFO mode........................................................................................................ 26
4.2.4 Auto RS485 Operation ............................................................................................................................. 26
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