参数资料
型号: XR17V354IB176-F
厂商: Exar Corporation
文件页数: 34/66页
文件大小: 0K
描述: IC UART PCIE 256B QUAD 176FPBGA
产品培训模块: PCIe UARTs
标准包装: 160
特点: *
通道数: 4,QUART
FIFO's: 256 字节
规程: RS485
电源电压: 3.3V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 176-LFBGA
供应商设备封装: 176-FPBGA(13x13)
包装: 托盘
其它名称: 1016-1472
XR17V354IB176-F-ND
XR17V354
4
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.3
RX2
B9
I
UART channel 2 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
RTS2#
A9
O
UART channel 2 Request to Send or general purpose output (active LOW).
CTS2#
C8
I
UART channel 2 Clear to Send or general purpose input (active LOW).
DTR2#
B8
O
UART channel 2 Data Terminal Ready or general purpose output (active
LOW).
DSR2#
A7
I
UART channel 2 Data Set Ready or general purpose input (active LOW).
CD2#
B7
I
UART channel 2 Carrier Detect or general purpose input (active LOW).
RI2#
C7
I
UART channel 2 Ring Indicator or general purpose input (active LOW).
TX3
N5
O
UART channel 3 Transmit Data or infrared transmit data.
RX3
R5
I
UART channel 3 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
RTS3#
P5
O
UART channel 3 Request to Send or general purpose output (active LOW).
CTS3#
N6
I
UART channel 3 Clear to Send or general purpose input (active LOW).
DTR3#
P6
O
UART channel 3 Data Terminal Ready or general purpose output (active
LOW).
DSR3#
R6
I
UART channel 3 Data Set Ready or general purpose input (active LOW).
CD3#
N7
I
UART channel 3 Carrier Detect or general purpose input (active LOW).
RI3#
N8
I
UART channel 3 Ring Indicator or general purpose input (active LOW).
EXPANSION INTERFACE
MODE
G15
I
Expansion Interface Mode Select. Connect this pin to VCC to enable master
mode or when there is no slave device. Connect this pin to GND when the
device is in slave mode.
CLK
G14
I/O
Expansion Interface Clock. In master mode, this pin is the clock output to the
slave device. In slave mode, this pin is the clock input from the master
device. The expansion interface clock is 62.5MHz. The UARTs on the slave
device will need to use different baud rate generator divisors than the master
device. The trace capacitance between the master and slave device must be
less than 25pF.
D7
F15
I/O
Expansion Interface Data 7 (MSB). The trace capacitance between the mas-
ter and slave device must be less than 25pF.
D6
F14
I/O
Expansion Interface Data 6. The trace capacitance between the master and
slave device must be less than 25pF.
D5
F13
I/O
Expansion Interface Data 5. The trace capacitance between the master and
slave device must be less than 25pF.
D4
E15
I/O
Expansion Interface Data 4. The trace capacitance between the master and
slave device must be less than 25pF.
PIN DESCRIPTIONS
NAME
PIN #TYPE
DESCRIPTION
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